One Check Fail Byte Scheme for NAND Memory Programming
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Solution Overview
Problem
Conventional memory device programming algorithms in NAND architecture require multiple evaluations of failure bytes at every program pulse stage, leading to inefficiency and increased programming time due to excessive logic overhead.
Innovation Solution
Implementing a unified one progressive check of failure bytes, where a single failure byte check is performed for each level except the last, eliminating the need for checks at subsequent stages and reducing programming time by optimizing the tolerance level and program operation sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple evaluations of failure bytes are performed at every program pulse stage, then programming reliability is improved, but programming time increases due to excessive logic overhead
Solution Approach 1:
The patent extracts the failure byte check operation from every program pulse stage and consolidates it to occur only once per level. This removal of redundant checks from intermediate stages eliminates excessive logic overhead while preserving the essential verification function, thereby reducing programming time without sacrificing programming reliability.
Solution Approach 2:
The patent performs failure byte checks in advance at level boundaries rather than continuously during each program pulse stage. By conducting verification preliminarily at strategic points (once per level), the system ensures programming reliability is maintained while avoiding the time penalty of continuous evaluation throughout the programming process.
2Manufacturing precision
If multiple evaluations of failure bytes are performed at every program pulse stage, then programming accuracy is improved, but device complexity increases due to excessive logic overhead
Solution Approach 1:
The patent removes redundant failure byte check operations from intermediate program pulse stages, extracting only the essential verification function. This reduction in check frequency decreases logic overhead and device complexity while maintaining programming accuracy by preserving verification at critical level boundaries.
Solution Approach 2:
By performing failure byte checks preliminarily at level boundaries rather than continuously, the patent reduces the complexity of the programming logic. The preliminary check approach maintains programming accuracy through verification while significantly reducing the logical complexity compared to continuous evaluation at every pulse stage.
Data Source
AI summary
Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.