ONO Memory Cell Periodic Voltage Control
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Solution Overview
Problem
Existing flash memory cell technologies face challenges in controlling threshold voltage distributions during programming and erasing operations, leading to over-programming and over-erasing issues, which result in wide voltage distributions and potential errors in multi-level memory cells.
Innovation Solution
Applying alternating constant voltages to the control gate and doping regions, with different voltage values for programming and erasing operations, to prevent over-programming and over-erasing by interrupting the voltage application and switching between higher and lower voltages cyclically, thereby narrowing the threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If constant voltage is applied to the control gate during programming/erasing operations, then the programming/erasing speed is improved, but the threshold voltage distribution becomes wide leading to over-programming and over-erasing
Solution Approach 1:
The patent applies periodic voltage pulses to the control gate instead of constant voltage. The method involves applying a first constant voltage for a first period, then a second constant voltage for a second period, repeating this cycle. This periodic action allows fast programming/erasing while controlling the threshold voltage distribution by interrupting the voltage application periodically.
Solution Approach 2:
The patent dynamically adjusts the voltage applied to the control gate by switching between different voltage levels (first constant voltage and second constant voltage) at different time periods. This dynamic voltage adjustment prevents over-programming and over-erasing while maintaining high programming/erasing speed.
2Productivity
If high voltage is applied to inject electrons into the nitride layer, then the programming speed is improved, but the threshold voltage distribution widens causing over-programming
Solution Approach 1:
The patent uses periodic voltage pulses to inject electrons into the nitride layer. By applying high voltage for a first period and then a different voltage for a second period in repeated cycles, the method achieves fast electron injection while controlling the threshold voltage distribution to prevent over-programming and ensure data storage accuracy.
3Productivity
If high voltage is applied to remove electrons from the nitride layer, then the erasing speed is improved, but the threshold voltage distribution widens causing over-erasing
Solution Approach 1:
The patent applies periodic voltage pulses to the control gate during erasing operations. By cycling between a first constant voltage for a first period and a second constant voltage for a second period, the method achieves fast electron removal from the nitride layer while controlling the threshold voltage distribution to prevent over-erasing and maintain data storage accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively narrows the threshold voltage distribution, preventing over-programming and over-erasing, ensuring more reliable data storage and read operations by controlling the electron and hole injection rates into the nitride layer.
Implementation Method 1
Programming operations (i.e., charge injection) on a flash memory cell may be carried out by various methods, such as channel hot electron (CHE) injection or Fowler-Nordheim (FN) injection, both of which inject electrons into the nitride layer 212
Implementation Method 2
Erasing operations (i.e., charge removal) may be accomplished by band-to-band hot hole tunneling (BTBHHT) or Fowler-Nordheim (FN) injection
Data Source
AI summary
A method for performing operations on a memory cell is described. The memory cell includes a substrate, a first doping region and a second doping region. The first doping region and the second doping region are formed on the substrate with a channel region therebetween. A dielectric layer is formed above the channel region and a conductive gate is formed over the dielectric layer. The method includes applying a first constant voltage for a first period to the conductive gate followed by applying a second constant voltage for a second period to the conductive gate repeatedly. The value of the first constant voltage is different from the value of the second constant voltage. A third constant voltage and a fourth voltage are applied to the first doping region and the second doping region respectively.


