On-Chip Light Sensing Device for High-Speed Image Processing
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Solution Overview
Problem
Existing sensing arrays face inefficiencies in correcting for variability and noise, particularly in high-speed imaging applications where software-based non-uniformity correction is energy and resource-intensive, limiting their ability to perform accurately and efficiently in real-time.
Innovation Solution
The implementation of a flexible readout and integrated sensor (FRIS) system-on-chip light sensing device with high sampling rates (over 10,000 frames per second) that performs on-chip image data processing, including signal conditioning, local gain control, and auto-detection, enabling high-speed imaging and precise measurements through structured lighting and optical flow analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If software-based non-uniformity correction is applied after reading out sensing elements to external memory, then variability correction can be performed, but energy consumption and resource usage increase significantly
Solution Approach 1:
The patent combines the sensing elements with signal processing circuitry directly at the focal plane, merging the functions of light detection and signal conditioning into a single integrated structure. This eliminates the need to transfer raw data to external memory for processing, thereby reducing energy consumption while maintaining correction accuracy.
Solution Approach 2:
The patent performs variability correction and signal processing operations before the data leaves the sensing array. By applying gain control and non-uniformity correction at the source rather than in post-processing, the system achieves the same measurement precision with significantly lower energy expenditure.
2Measurement precision
If software-based non-uniformity correction is applied after reading out sensing elements, then variability can be corrected, but processing time and resource efficiency deteriorate
Solution Approach 1:
The sensing elements are integrated with signal processing circuitry at the focal plane, allowing simultaneous detection and correction operations. This parallel processing architecture eliminates sequential bottlenecks and significantly improves processing efficiency while maintaining correction accuracy.
Solution Approach 2:
Signal conditioning and variability correction are performed immediately upon signal generation at the sensing elements, before data needs to be transferred externally. This preliminary processing approach eliminates waiting time and improves overall system productivity.
3Productivity
If high sampling rates greater than 10,000 frames per second are implemented, then high-speed imaging capability is achieved, but energy consumption and resource requirements increase
Solution Approach 1:
The integration of sensing elements with signal processing circuitry at the focal plane enables high-speed sampling without requiring external processing resources. The on-chip circuitry handles high-rate data generation and processing efficiently, reducing the energy overhead associated with high sampling rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate 3D scene measurement, boundary violation detection, and speed measurement with reduced energy consumption and resource usage, allowing for efficient operation in applications requiring high-speed imaging, such as sports monitoring and security systems.
Implementation Method 1
an illuminator assembly configured to generate a structured light pattern
Implementation Method 2
a system-on-chip light sensing device having sensors disposed to receive reflected light emitted by the illuminator assembly
Data Source
AI summary
A scene measurement assembly includes a first illuminator assembly having multiple grids of coplanar illuminators, a first system-on-chip light sensing device having sensors disposed to receive reflected light emitted by the first illuminator assembly, a second illuminator assembly having plural grids of coplanar illuminators, each of the plural grids of coplanar illuminators being disposed in different planes relative to each other, and a second system-on-chip light sensing device that receives reflected light emitted by the second illuminator assembly. Each of the multiple grids of coplanar illuminators of both illuminator assemblies is disposed in different planes relative to each other. The first and second system-on-chip light sensing devices each have a sampling rate of greater than 10,000 frames per second relative to performing on-chip image data processing. The system-on-chip light sensing devices are each disposed at a scene to be measured at locations having different perspectives of the scene.