Op-Amp Offset Trim Using R-2R Ladder RDAC Circuits
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Solution Overview
Problem
Conventional methods for trimming offset voltage in operational amplifiers require large binary-weighted resistors, leading to increased costs and circuit size due to the use of binary-weighted resistor sets for trimming resistance or current.
Innovation Solution
The implementation of resistive digital-to-analog converter (RDAC) and current digital-to-analog converter (IDAC) circuits using an R-2R ladder structure, which eliminates the need for binary-weighted resistors, reducing the overall trim circuit size and cost by using a trim code to control switches and adjust resistance or current accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If binary-weighted resistors are used for trimming offset voltage, then trimming precision is improved, but circuit size and manufacturing cost increase
Solution Approach 1:
The patent changes the resistance values of resistors in the trim circuit based on a trim code to adjust and trim the offset voltage. By varying resistance parameters according to digital code values, the circuit achieves precise offset trimming without requiring large binary-weighted resistor sets, thus resolving the contradiction between trimming precision and circuit size
Solution Approach 2:
The patent uses a simplified resistor configuration that replicates the trimming function of complex binary-weighted resistors. Instead of implementing full binary-weighted resistor networks, the invention uses a reduced set of resistors with specific value relationships that copy the essential trimming capability while significantly reducing circuit area
2Measurement precision
If binary-weighted resistors are used for trimming offset voltage, then trimming precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the resistance values of resistors in the trim circuit based on a trim code to adjust and trim the offset voltage. By varying resistance parameters according to digital code values, the circuit achieves precise offset trimming without requiring large binary-weighted resistor sets, thus resolving the contradiction between trimming precision and circuit size
Solution Approach 2:
The patent uses a simplified resistor configuration that replicates the trimming function of complex binary-weighted resistors. Instead of implementing full binary-weighted resistor networks, the invention uses a reduced set of resistors with specific value relationships that copy the essential trimming capability while significantly reducing circuit area
Data Source
AI summary
An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.