Analogue/Digital Conversion TRIZ Cases

Timed ADC sampling and half-duplex isolated feedback improve switching reliability, noise immunity, and data integrity in power stages.

Histogram-based threshold adaptation preserves weak encoded RF signals while suppressing interference and AGC-related data loss.

Digital baseband processing replaces the RF Butler matrix to correct gain and phase errors, suppress signal leakage, and improve throughput.

Gradual multi-trigger pulse transitions improve edge detection under common mode noise in capacitive isolation signal transmission.

Standard deviation feedback calibrates TIADC clock skew without a reference ADC, improving ENOB and SNR while lowering power use.

Integrated voltage data comparison generates flag signals during imaging, helping detect power supply issues before malfunctions occur.

A pseudo-detection path mirrors sensor A/D conversion so signal comparison can detect circuit failures during normal operation.

Segmented DSP and CPU processing clarifies sensor data flow while improving temperature correction and failure diagnosis accuracy.

Threshold-crossing timing with reversed bridge excitation improves sensor digitization accuracy and adds built-in error detection.

Local reference signals and frequency indication enable synchronized multi-sensor digital sampling with lower energy use and less hardware complexity.

A digital error-feedback PWM amplifier cuts analog circuit area while improving noise and distortion in automotive audio output.

Series MOS switches and a potential holding capacitor suppress hold-period charge leakage to keep switched-capacitor amplifier output stable.

Combined smoke and temperature threshold logic cuts false alarms while preserving prompt fire detection and reducing wasted emergency response.

A sigma-delta ADC and DAC feedback loop cancels electret microphone DC bias, avoiding large AC coupling capacitors and ADC overload.

Switching elements, capacitors, and clock recovery help decode ISI-distorted differential signals while preserving bandwidth in high-speed receivers.

A level shift circuit expands comparator output swing in solid-state imaging elements to avoid inverter malfunction, leakage current, and design limits.

A buffer-driven bootstrapped switch keeps gate-source voltage stable to cut harmonic distortion and raise ADC sampling frequency.

A shared SAR reference and selective comparator disabling cut column AD conversion area and power while preserving speed for top-K searches.

Multi-stage digital and analog gain with noise gating boosts audio to piezo-speaker voltage while preserving dynamic range and reducing noise.

A toggling gate-bias and integrated drain-current signal locates the local minimum faster than voltage sweeping with less hardware complexity.

Double correlation sampling with switched capacitors cancels amplifier offset in encoder front ends, improving position accuracy and dynamic range.

Two comparators with different capacitor gains extend image-sensor ADC dynamic range across changing illuminance while preserving sensitivity.

Clock-state detection switches feedback resistance to adapt isolation amplifier input range without extra terminals or larger packages.

Adaptive excitation frequency selection minimizes narrow-band noise in inductive position sensing, improving precision and temporal resolution.

A coarse histogram finds the peak bin, then a fine histogram zooms into that depth range to improve TDC resolution with fewer bins, less area, and lower power.

An integrator and counter convert photodiode current with 119 dB dynamic range while cutting power and component count in PPG and fNIRS sensing.

Range-specific gain and offset control lets one sensor front end improve accuracy, avoid amplifier saturation, and cut oversampling power.

Cascaded Mach-Zehnder modulators and photodiodes extend DAC bandwidth while preserving SNR and dynamic range for higher waveform fidelity.

A cascaded two-stage pass transistor circuit selects wide grayscale signal ranges while reducing circuit area and suppressing selection noise.

Forcing known integrator inputs and fixed duty cycles lets this PWM amplifier isolate offsets and resistor mismatches before distortion grows.

A dual-path readout combines frame-based analog integration with 10KHz digital change detection to raise video frame rate without larger pixel circuits.

A DAC input stage, loop filter, quantizer, and feedback path reduce op-amp count and power use while preserving audio amplification.

Dual-resolution ADCs in event-detection pixels improve image quality and reduce noise without separate imaging elements.

Calibration-based correction values compensate eccentricity and tumbling errors in reflection grating angle measurement.

Differential on-chip sampling reconstructs transient settling behavior without external probing, using low-resolution ADC conversion for simpler IC monitoring.

A stored residual voltage and dummy-voltage comparison correct noisy digital pixel counter readout while reducing calibration power.

A real-coefficient baseband FIR with rotator and derotator corrects DAC roll-off while cutting filter complexity and power use.

Dual reference signals and differential comparison cut DAC power in image-sensor ADCs without degrading PSNR.

Delayed filter replicas interpolate sampled data to build accurate eye diagrams without timing shifts or extra ADC and DSP hardware.

A charge-pump differential converter helps silicon microphone PGAs improve signal-to-noise ratio and reject power supply noise.

Polynomial digital compensation linearizes a silicon microphone, cutting distortion while preserving signal-to-noise ratio.

GPS time stamps align independently clocked recording units, correcting FFT phase mismatch for accurate cross-spectrum analysis over distance.

AC-coupled common-mode feedback removes the tail current source to widen output swing, cut offset errors, and boost pipelined ADC accuracy.

R-2R ladder RDAC and IDAC trim circuits replace binary-weighted resistors to cut op-amp offset trim area and cost while keeping precision.

Per-sensor calibration sets ADC reference voltage and divider resistance to match sensor variation, improving pressure measurement accuracy.

Passive difference detection and reset control cut event-driven pixel power use while improving uniformity, linearity, and noise performance.

Half-duplex capacitive coupling and timed ADC sampling deliver real-time power-stage feedback with lower noise, area, and power use.

A neural network corrects sigma-delta ADC nonlinearity and manufacturing errors, improving SNDR without extra analog calibration hardware.

Negative capacitance cancels comparator output parasitics, shortening access time and enabling higher-frequency sigma-delta conversion.

Embedding chirp start in the distributed clock lets cascaded ICs align ADC sampling with lower phase error and fewer PCB constraints.