Pixel Readout Circuit for High-Frame-Rate Imaging Updates
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Solution Overview
Problem
Conventional video imaging readout circuits are limited in achieving high frame rates due to practical limitations of analog circuits and require complex digital processing, which severely limits pixel density and increases costs.
Innovation Solution
A readout circuit with pixel integration circuits operating at hundreds of Hertz for analog signal integration and pixel derivation circuits operating at 10KHz for digital data output, allowing for high frame rate video capture and reconstruction with compact digital derivation circuitry, enabling high pixel density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional analog readout circuits are used, then the circuit structure is simple, but the achievable frame rate is limited to hundreds of Hertz
Solution Approach 1:
The readout circuit is segmented into two independent paths: an analog integration path for standard video output and a digital event detection path for high-speed frame capture. This segmentation allows each path to be optimized independently, enabling high frame rates in the digital path without compromising the simplicity of the analog path.
Solution Approach 2:
The system dynamically switches between analog and digital processing modes based on the required frame rate. For standard video rates, the analog path is used; for high frame rates up to 10KHz, the digital path is activated. This dynamic adaptation resolves the contradiction by providing different processing modes for different performance requirements.
2Speed
If digital in-pixel processing is implemented to achieve high frame rates, then the frame rate can be increased, but the pixel density is severely limited due to larger circuit area
Solution Approach 1:
The pixel array is segmented into pixels with full readout capability and shared pixels that only perform event detection. This segmentation allows the majority of pixels to remain small while a smaller subset provides high-speed digital output, resolving the area-frame rate contradiction.
Solution Approach 2:
The readout circuit is designed with multi-functionality to handle both standard video output and high-speed event detection. The same physical infrastructure supports both analog integration for video and digital counting for high-frame-rate capture, eliminating the need for separate dedicated hardware and reducing overall pixel area requirements.
3Measurement precision
If digital in-pixel processing with high bit depth is used, then the video quality is improved, but the number of output bit lines increases, further limiting pixel density
Solution Approach 1:
Instead of implementing full high-bit-depth digital processing for every pixel, the system uses partial digital processing only where needed for event detection. The digital path provides sufficient precision for detecting changes and counting events, while the analog path handles full video quality output, avoiding the need for extensive high-bit-depth digital infrastructure across the entire array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high frame rate video capture (up to 10KHz) with high pixel density (100 µm² and below) while reducing the number of bit lines required, facilitating efficient video reconstruction and processing.
Implementation Method 1
The capacitive unit is controllably linked to input channel for accumulating charge corresponding to received intensity generated by said pixel during a single frame period
Implementation Method 2
an input channel for receiving an image signal corresponding to electrical output of a photosensitive element of the pixel
Data Source
Figure 1A
Figure 1B~1D
Figure 2A~2B
AI summary
A pixel readout circuit and a technique for imaging are disclosed. The readout circuit includes: (A) an array of pixel integration circuits, each adapted for receiving an electric signal indicative of photocurrent of light sensitive pixel of a pixel matrix, integrate the electric signal over a frame period, and output the integrated signal at an imaging frame rate being one over the frame period; and (B) an array of pixel derivation circuits, each includes a signal preprocessing channel for receiving a total electric signal indicative of at least a component of the photocurrent(s) of a cluster of one or more respective light sensitive pixels of the pixel matrix; and a comparison unit adapted to analyze the total electric signal to determine digital data indicative of a change in the total electric signal relative to one or more thresholds; and a digital output utility adapted to readout of the digital data at a second rate different than the imaging frame rate. An image/video processing technique is disclosed comprising: processing the integrated signals of each frame period, to yield a video data comprising image frames at the imaging frame rate; and, updating the values of pixels in the image frames of the video, based on the digital data provided at the second rate, to thereby obtain an updated video with frame rate higher than the imaging frame rate.