Shared Comparator Circuit for Low-Power Column AD Conversion
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Solution Overview
Problem
Current computation systems using neural networks face challenges in reducing circuit area and power consumption while maintaining operation speed, particularly in implementing AD converters for each column, which consume high power and occupy large areas, and alternative solutions like WTA or SS type AD converters suffer from low resolution and timing restrictions.
Innovation Solution
The computation system employs a SAR type AD conversion process using a common DA conversion unit, gradually disabling comparators based on AD conversion results, and performs parallel processing to search for maximum, top K, minimum, or bottom K values, thereby reducing circuit area and power consumption while increasing operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If AD converters are implemented for each column, then measurement precision is improved, but power consumption increases and device area increases
Solution Approach 1:
Multiple AD converters are merged into a single shared AD converter that is time-multiplexed across multiple columns. The system sequentially serves different columns with one converter, reducing the total number of converters from N (one per column) to 1, thereby dramatically reducing power consumption while maintaining the required conversion precision for each column.
Solution Approach 2:
The single AD converter is designed to perform multiple functions by serving different columns at different time slots. This universal converter handles AD conversion for all columns sequentially, making one device perform the work of multiple dedicated converters, thus reducing overall power consumption without sacrificing measurement precision.
2Measurement precision
If AD converters are implemented for each column, then measurement precision is improved, but device area increases
Solution Approach 1:
Multiple AD converters are merged into a single shared AD converter that is time-multiplexed across multiple columns. This consolidation reduces the total circuit area occupied by AD conversion functionality from N separate converter blocks to one shared block, while the required precision is maintained through dedicated conversion cycles for each column.
Solution Approach 2:
The system transitions from a spatial distribution of AD converters (one per column in parallel) to a temporal distribution (one converter serving multiple columns sequentially). This dimensional shift from space to time allows the same precision to be achieved with significantly reduced hardware area by utilizing time-multiplexing.
3Area of stationary object
If WTA or SS type AD converters are used, then device area is reduced, but measurement precision deteriorates
Solution Approach 1:
The patent extracts the AD conversion function from specialized low-precision circuits (WTA or SS type) and implements it using a full-precision conventional AD converter. By taking out the conversion function and applying it with proper time-multiplexing and digital processing, the system achieves high measurement precision while still maintaining reduced area through sharing the converter across multiple columns.
Solution Approach 2:
The system changes the operational parameters of the shared AD converter by implementing time-multiplexed operation with proper sequencing. Instead of using continuously operating low-precision converters, the patent uses a single high-precision converter with controlled activation timing, thereby achieving both area reduction and high precision through parameter optimization rather than hardware reduction.
4Area of stationary object
If WTA or SS type AD converters are used, then device area is reduced, but productivity deteriorates due to timing restrictions
Solution Approach 1:
The shared AD converter operates continuously in a time-multiplexed manner, serving different columns in sequential batches without idle gaps. By optimizing the conversion scheduling and using parallel preprocessing stages, the system maintains continuous useful action across all columns, achieving high productivity despite using a single converter instead of multiple parallel converters.
Data Source
AI summary
According to one embodiment, in a processing circuit of a computation system, a plurality of comparators corresponds to the respective columns, each including a first input node, a second input node, and an output node, the first input node receiving any one of the second signals, the second input node receiving a signal corresponding to a global reference signal provided to each second input node, the output node outputting a local signal. A global circuit is provided common to the plurality of comparators, the global circuit generating a global signal according to a plurality of the local signals, the global circuit generating the global reference signal by an SAR method according to the global signal. The processing circuit disables some of the plurality of comparators according to the local signals and the global signal.