Time-Interleaved ADC Front End for ISI-Affected Receiver Signals
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Solution Overview
Problem
High-speed serial communication systems face challenges in accurately decoding data from differential signals that have undergone inter-symbol interference due to transmission path losses, which affect the performance of semiconductor integrated circuits in receiver devices.
Innovation Solution
The semiconductor integrated circuit employs a time-interleaved ADC with a sampling front end that includes switching elements and capacitors, along with a clock data recovery circuit, to process and recover the original data from the interfered signals by utilizing clock signals and reference voltages, effectively compensating for transmission path characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional ADC is used to process differential signals, then the circuit complexity is lower, but the bandwidth and distortion performance deteriorate at high speeds
Solution Approach 1:
The ADC is divided into multiple sub-ADCs that operate in parallel with time-interleaved sampling. Each sub-ADC processes a portion of the sampling cycles, allowing the overall system to achieve higher effective sampling rates and bandwidth without requiring a single complex high-speed converter
Solution Approach 2:
The circuit employs dynamic element matching (DEM) that randomly swaps capacitor connections during tracking mode to distribute quantization errors and reduce distortion. This dynamic reconfiguration maintains signal integrity while managing the complexity of high-speed conversion
2Speed
If the sampling frequency is increased to handle high-speed signals, then the bandwidth improves, but the distortion increases due to inter-symbol interference
Solution Approach 1:
The ADC operates in periodic alternating modes: tracking mode for signal following and holding mode for sampling. This periodic switching between modes allows the circuit to adapt to high-frequency signals while maintaining accuracy through controlled sampling intervals
Solution Approach 2:
The tracking mode provides continuous feedback where the capacitor follows the input signal, enabling the circuit to compensate for transmission path distortions and maintain signal integrity before the actual sampling operation
3Measurement precision
If time-interleaved ADC architecture is used to improve bandwidth, then the distortion reduces, but the device complexity increases
Solution Approach 1:
Multiple sub-ADCs are merged into a single time-interleaved architecture where each sub-ADC shares common components such as the differential input stage and capacitor array. This merging approach achieves the benefits of parallel processing while reducing overall component count and complexity
Data Source
AI summary
According to one embodiment, a semiconductor integrated circuit includes: a first buffer including an input end to which a first signal is configured to be supplied; a first switching element including a first end coupled to an output end of the first buffer and a second end coupled to a first node; a first capacitor including a first end coupled to the first node and a grounded second end; a second switching element including a first end coupled to the first node and a second end coupled to a second node; a second buffer including an input end coupled to the second node; and a first converter configured to determine a first bit string from a first output from the second buffer. The first and second switching elements being configured to switch between states based on a first clock signal.