TIADC Clock Skew Calibration Using Standard Deviation Feedback
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Solution Overview
Problem
Existing time-interleaved analog-to-digital converters (TIADCs) face challenges in calibrating clock skew, which leads to increased standard deviations and variances in sampled data, affecting performance indices like ENOB and SNR.
Innovation Solution
The proposed solution involves an apparatus with an analog-to-digital conversion circuit, a skew detection circuit that calculates and compares sums of standard deviations or variances, and a compensation circuit that adjusts the clock signal based on the selected smaller value to compensate for clock skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If clock skew calibration is performed using existing methods, then measurement precision may be maintained, but device complexity increases due to requiring reference ADC
Solution Approach 1:
The patent extracts and removes the reference ADC component from the calibration system. Instead of using a separate reference ADC to measure clock skew, the invention uses the existing ADC output signals directly to calculate standard deviation, thereby simplifying the device structure while maintaining calibration functionality
Solution Approach 2:
The system performs self-calibration by using its own output signals to detect and correct clock skew. The ADC outputs are fed back to the skew detection circuit which calculates standard deviation and generates calibration signals, eliminating the need for external reference components
2Productivity
If parallel-connected ADCs are used to increase sampling rate, then productivity is improved, but clock skew increases leading to worsened measurement precision
Solution Approach 1:
The patent implements a feedback mechanism where the ADC output signals are continuously monitored by the skew detection circuit. The calculated standard deviation is fed back to generate calibration signals that adjust the sampling clocks, creating a closed-loop system that maintains precision despite high-speed parallel operation
Solution Approach 2:
The system dynamically adjusts clock phase parameters based on real-time standard deviation calculations. By changing the timing parameters of the sampling clocks in response to detected skew, the system maintains optimal performance across varying operating conditions
Data Source
AI summary
An apparatus and method for timing skew calibration. For example, the apparatus may include an analog-to-digital conversion circuit configured to sample an input signal based on a clock signal and convert the sampled input signal into a digital code, a skew detection circuit configured to calculate a first sum of standard deviations for respective levels of the digital code, compare the first sum of the standard deviations with a previously calculated second sum of standard deviations, and select a smaller value from among the first sum and the second sum, and a compensation circuit configured to compensate for a skew of the clock signal based on the selected one of the first sum and the second sum.