Opaque Bridge for PCIe Bus Number Translation
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Solution Overview
Problem
PCIe bus systems often face compatibility issues due to limited bus numbers, which can prevent the construction of desired systems, as they typically only offer eight bits for setting bus numbers, leading to discontinuities that break the routing mechanism and result in insufficient contiguous bus numbers for large PXI Express chassis applications.
Innovation Solution
A mechanism is introduced to reset bus numbers and translate Bus Device Functions (BDFs) during operation, allowing for the introduction of discontinuities in bus numbers while ensuring the system functions properly and maintaining full bus configuration functionality, using a non-transparent bridge (NTB) to couple hosts to PCIe subsystems and route packets based on packet type, rather than just address information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If standard PCIe bus numbering with eight bits is used, then the system maintains simple address routing, but the system lacks sufficient contiguous bus numbers for large PXI Express chassis applications
Solution Approach 1:
An opaque bridge is introduced as an intermediary device between the host and PCIe subsystems. The bridge receives packets from the host, translates their destination BDFs to different values, and forwards them to the appropriate subsystem. This intermediary enables the system to support more than eight contiguous bus numbers by decoupling the host's view of bus numbering from the actual subsystem numbering, resolving the contradiction between maintaining simple routing and supporting large quantities of bus numbers.
2Quantity of substance
If bus numbers are reset to accommodate more devices, then more contiguous bus numbers become available, but the routing mechanism breaks due to discontinuities
Solution Approach 1:
The opaque bridge acts as a mediator that translates BDFs between the host and subsystems. When bus numbers are reset to accommodate more devices, the bridge translates the destination BDFs in incoming packets to appropriate values for the reset numbering scheme, ensuring continuous and reliable routing despite the numbering discontinuity from the host's perspective.
Solution Approach 2:
The system changes the BDF parameter values translated by the opaque bridge depending on the operational state. When subsystems are reset or reconfigured, the bridge dynamically adjusts its translation mappings to maintain correct routing, allowing bus numbers to be reset while preserving routing reliability through parameter transformation.
3Adaptability or versatility
If a non-transparent bridge is used to couple hosts to PCIe subsystems, then packet routing is enabled with BDF translation, but the system complexity increases
Solution Approach 1:
The opaque bridge introduces controlled complexity as an intermediary that provides BDF translation capabilities. This complexity is localized to the bridge device, allowing the host and subsystems to maintain their existing simple architectures while gaining the versatility to configure large-scale systems with more than eight bus numbers through the bridge's translation functionality.
Data Source
AI summary
A host system may couple to a PCIe subsystem. During setup of the PCIe subsystem, the BIOS in the host system may first be informed that the devices to be coupled are not PCIe devices, and certain amount of memory is required for these devices. The BIOS may therefore not attempt to configure the devices, and may instead allocate the required memory space. When the operating system boots up, it may not attempt to configure the devices, loading a custom driver instead of an existing PCI driver to configure the bus. Once loaded, the custom driver may configure the devices, then inform the OS that there are PCIe devices in the system at the specified addresses, which may cause the OS to load and execute existing PCIe device drivers to operate/use the devices. The proprietary driver may also be used to handle traffic between the PCIe drivers and the OS.