Open-Drain Output Circuit With Balanced I2C Edge Delays
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Solution Overview
Problem
Conventional open drain output circuits for I2C bus interfaces do not adequately match the delay times for rising and falling output signals, leading to bus errors due to insufficient adjustment mechanisms for the rising characteristic, resulting in output signals DATA OUT rising before CLOCK OUT falls, despite synchronized input signals.
Innovation Solution
Incorporation of delay time adjustment circuits, including P-channel MOS transistors and resistors, to balance the delay times for both rising and falling output signals, ensuring compliance with I2C bus interface standards by adjusting the resistance and capacitance values to synchronize the output signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gradient for the fall of the output signal is set to be gradual to comply with I2C bus standards, then the falling characteristic meets the standard, but the delay time from input transition to output transistor turn-off increases
Solution Approach 1:
The patent divides the delay adjustment into two independent segments: one for the falling edge (using capacitor C1 and resistor R1) and one for the rising edge (using capacitor C3 and resistor R3). This segmentation allows each edge to be optimized independently, resolving the contradiction by enabling gradual falling gradient compliance while minimizing rising edge delay through separate adjustment mechanisms.
Solution Approach 2:
The patent employs parameter changes by adjusting capacitance values (C1, C3) and resistance values (R1, R3) to control the delay times. By changing these electrical parameters, the circuit achieves both gradual falling characteristics for standard compliance and minimized delay times for responsive operation.
2Manufacturing precision
If the resistance of resistor R1 is adjusted to set the output signal gradient, then the falling characteristic complies with I2C standards, but the delay time difference between rising and falling output signals increases
Solution Approach 1:
The patent introduces asymmetry by adding a dedicated rising edge delay adjustment circuit (capacitor C3 and resistor R3) that mirrors the falling edge circuitry. This asymmetric addition to the original falling-edge-only adjustment enables independent optimization of both edges, allowing gradient compliance while balancing delay times through separate control mechanisms.
Solution Approach 2:
The patent applies preliminary action by pre-adjusting the delay times for both rising and falling edges using the capacitor-resistor networks before signal transmission. This preliminary adjustment ensures that delay time differences are minimized in advance, preventing bus errors while maintaining gradient compliance throughout operation.
3Reliability
If delay time adjustment circuits are added to balance rising and falling delay times, then I2C bus interface stability improves, but device complexity increases
Solution Approach 1:
The patent uses copying by replicating the delay adjustment mechanism for the rising edge (capacitor C3 and resistor R3) based on the existing falling edge circuit (capacitor C1 and resistor R1). This copying approach provides a systematic solution that improves reliability through balanced delay times while keeping the added complexity manageable through pattern repetition.
Data Source
AI summary
An open drain output circuit for use as an I2C bus interface. The open drain output circuit includes an output terminal. An input unit performs a first operation causing the potential at the output node to steeply fall and a second operation for gradually raising the potential in accordance with transition of an input signal. An output transistor connected to the output node of the input unit and the output terminal is turned OFF in the first operation and turned ON in the second operation. A delay time adjustment circuit reduces the difference between a delay time from transition of the input signal until when the output transistor is turned OFF in the first operation and a delay time from transition of the input signal until when the output transistor is turned ON in the second operation.