Open Resistive Memory Array Layout for DDR-Speed Low-Power Reads
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Solution Overview
Problem
Current resistive change memory arrays face limitations in achieving high speed and low power consumption, making them incompatible with certain DDR memory interfaces due to timing and power requirements.
Innovation Solution
A DDR-compatible circuit architecture for resistive change element memory arrays is developed, featuring a folded bit line arrangement, reference elements, and sense amplifiers that allow for rapid reading and low-power programming by comparing discharge rates between resistive change elements and reference elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional resistive change memory arrays are used, then non-volatile storage is achieved, but speed and power consumption are insufficient for DDR interface compatibility
Solution Approach 1:
The memory array is divided into multiple banks, each with independent sense amplifiers and bit line pairs. This segmentation allows parallel access to multiple memory cells simultaneously, increasing overall access speed while distributing power consumption across multiple smaller units, making DDR interface compatibility achievable
Solution Approach 2:
Reference elements are introduced as intermediary components to enable differential sensing. By comparing the discharge rates of selected resistive change elements against reference elements, the sense amplifiers can rapidly detect resistance states with lower power consumption, achieving both high speed and low power requirements for DDR interfaces
2Speed
If rapid reading is implemented, then access speed improves, but power consumption increases
Solution Approach 1:
The reading operation uses periodic discharge cycles where bit lines are pre-charged, then discharged through selected memory cells and reference elements. This periodic action enables rapid repeated readings at DDR speeds while the discharge-based mechanism inherently consumes less power than continuous sensing methods
Solution Approach 2:
The invention uses resistance state changes (analogous to color changes) as the sensing mechanism. By detecting resistance transitions through discharge rate comparisons rather than continuous current measurement, rapid reading is achieved with reduced power consumption, meeting DDR interface requirements
3Adaptability or versatility
If DDR interface compatibility is achieved, then speed and power requirements are met, but device complexity increases
Solution Approach 1:
The memory array uses universal building blocks (memory cells, sense amplifiers, bit line pairs, reference elements) that can be replicated and configured for different DDR interface modes. This modular universality allows the same basic architecture to achieve DDR compatibility without requiring entirely different circuit designs, managing complexity through standardization
Solution Approach 2:
Multiple functions are merged into the sense amplifier circuit, which simultaneously performs differential sensing, signal amplification, and data latching. By combining these functions into a single integrated circuit block rather than separate components, DDR interface compatibility is achieved while minimizing the increase in overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture enables faster and more energy-efficient operations, overcoming the limitations of existing technologies by allowing for rapid access and low-power reading and programming of resistive change memory elements, enhancing compatibility with DDR memory interfaces.
Implementation Method 1
Each memory cell within the array also comprises a selection device responsive to a control signal on a word line, wherein the selection device selectively provides a conductive path between a bit line and the second terminal of the resistive change element
Implementation Method 2
comparing the rate of discharge through the resistive change element to a reference value
Data Source
AI summary
A high-speed memory circuit architecture for arrays of resistive change elements is disclosed. An array of resistive change elements is organized into rows and columns, with each column serviced by a word line and each row serviced by two bit lines. Each row of resistive change elements includes a pair of reference elements and a sense amplifier. The reference elements are resistive components with electrical resistance values between the resistance corresponding to a SET condition and the resistance corresponding to a RESET condition within the resistive change elements being used in the array. A high speed READ operation is performed by discharging one of a row's bit lines through a resistive change element selected by a word line and simultaneously discharging the other of the row's bit lines through of the reference elements and comparing the rate of discharge on the two lines using the row's sense amplifier. Storage state data are transmitted to an output data bus as high speed synchronized data pulses. High speed data is received from an external synchronized data bus and stored by a PROGRAM operation within resistive change elements in a memory array configuration.