On-Package Memory Interconnect Layout for Bottom-Side Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit packages with on-package memory architectures face challenges in testing due to complex and costly procedures that require separate sockets for memory attachment, leading to increased size and signal length issues, which impact high-speed performance and customer customization.
Innovation Solution
The integration of memory interconnects that electrically couple memory pads on the top side of the package substrate to contacts on the bottom side, allowing memory to be socketed from the bottom during testing, reducing the need for a separate top-side socket and enabling a more compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate top-side socket is used for memory attachment during testing, then testing functionality is achieved, but package size and footprint increase
Solution Approach 1:
The patent combines the memory socket functionality with the existing substrate structure by routing memory interconnects through the substrate to provide test contacts on the bottom side. This eliminates the need for a separate top-side socket, merging the testing functionality into the existing package architecture and reducing overall package footprint.
Solution Approach 2:
The patent transitions the test contact interface from the top side (2D plane) to the bottom side of the substrate. By routing interconnects through the substrate thickness (adding the third dimension), the memory can be socketed from the bottom during testing, eliminating the need for additional top-side socket space.
2Reliability
If memory is socketed from the top side during testing, then testing is enabled, but signal length increases impacting high-speed performance
Solution Approach 1:
Instead of socketing memory from the top side as conventionally done, the patent inverts the approach by routing memory interconnects through the substrate to provide test contacts on the bottom side. This allows memory to be socketed from the bottom during testing, significantly reducing signal length and improving high-speed performance.
3Reliability
If complex testing procedures with separate sockets are used, then comprehensive testing is achieved, but device complexity increases
Solution Approach 1:
The substrate structure is designed to serve multiple functions: it provides mechanical support, electrical interconnects, and test interfaces. By routing memory interconnects through the substrate to create bottom-side test contacts, the same substrate structure enables both operational functionality and testing capability, reducing overall device complexity.
4Reliability
If memory is integrated on-package with top-side socketing, then memory functionality is achieved, but customer customization is limited
Solution Approach 1:
The patent separates the memory component from the processor package, allowing memory to be socketed independently during testing and enabling customers to customize their own memory configurations. The through-substrate interconnects provide the necessary electrical connection while maintaining customer adaptability and customization options.
Data Source
AI summary
Integrated circuit (IC) packages with On Package Memory (OPM) architectures are disclosed herein. An example IC package includes a substrate having a first side and a second side opposite the first side, a semiconductor die mounted on the first side of the substrate, and a die pad on the first side of the substrate. The die is electrically coupled to the die pad. The IC package also includes a memory pad on the first side of the substrate. The memory pad is to be electrically coupled to a memory mounted on the first side of the substrate. The IC package further includes a ball on the second side of the substrate, and a memory interconnect in the substrate electrically coupling the die pad, the memory pad, and the ball.