Opportunistic Multi-thread Processor Scheduling
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Solution Overview
Problem
Existing multi-threading techniques, such as SMT and token triggered multi-threading, face challenges in complexity and power consumption, leading to reduced processing efficiency and resource waste, particularly in embedded and low-power processors.
Innovation Solution
The opportunity-driven multi-threading method assigns clock cycles dynamically based on thread instruction readiness, using a thread instruction validity prediction circuit and two-dimensional thread identity registers to optimize thread execution and resource utilization, allowing previous threads to occupy unused cycles and avoid thrashing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SMT technique is used to improve processor operational capability, then processing efficiency is improved, but hardware complexity increases significantly
Solution Approach 1:
The patent implements dynamic thread scheduling where threads can be switched based on execution state rather than fixed time slots. The processor dynamically selects which thread to execute in each cycle based on readiness conditions, allowing flexible resource allocation that adapts to actual thread states, thereby improving efficiency without requiring complex fixed-time arbitration circuits.
Solution Approach 2:
The patent changes the operational mode parameter of processor resources between single-thread and multi-thread modes. Resources such as instruction caches and execution units can be shared among threads when in multi-thread mode, reducing the need for duplicate hardware structures. This parameter switching allows the system to achieve SMT-level efficiency with reduced hardware duplication compared to dedicated multi-thread architectures.
2Device complexity
If time-shared multi-threading is used to reduce hardware complexity and power consumption, then hardware complexity is reduced, but processing efficiency degrades
Solution Approach 1:
The patent ensures continuous useful action by allowing threads to be preempted and resumed without losing execution state. When a thread is switched out, its program counter and register states are preserved, enabling seamless resumption. This continuity mechanism ensures that threads spend minimal time in non-productive states, maintaining high processing efficiency even with time-shared resource allocation and simplified hardware.
3Reliability
If separate instruction caches are allocated to each thread to avoid thrashing, then thread execution is isolated, but memory resource waste increases
Solution Approach 1:
The patent makes instruction caches universal by allowing multiple threads to share the same cache structure. The cache is managed with thread-aware tagging that distinguishes between threads, enabling one cache to serve multiple threads simultaneously. This multi-functional cache design eliminates the need for separate caches per thread, reducing memory resource waste while maintaining thread isolation through software-managed cache coherence.
4Ease of operation
If fixed clock cycles are assigned to each thread, then thread execution is simplified, but clock cycles are wasted when threads cannot issue instructions
Solution Approach 1:
The patent implements a self-service mechanism where threads indicate their own readiness state and trigger their own execution. Each thread maintains a readiness flag that is automatically set when instructions are ready for execution. The scheduling logic simply checks these flags and activates threads that are ready, eliminating the need for complex centralized arbitration and avoiding wasted cycles by only activating threads that can productively use the clock cycle.
Data Source
AI summary
Disclosed are an opportunistic multi-thread method and processor, the method comprising the following steps: if a zeroth thread, a first thread, a second thread and a third thread all have instructions ready to be executed, then a zeroth clock period, a first clock period, a second clock period and a third clock period are respectively allocated to the zeroth thread, the first thread, the second thread and the third thread; if one of the threads cannot issue an instruction within a specified clock period because the instruction is not ready, and the previous thread still has an instruction ready to be executed after issuing certain instructions in the previous specified clock period, then the previous thread will take the specified clock period. The processor comprises an instruction cache, an instruction decoder, an instruction pipeline controller and an arithmetic logic unit; the opportunistic multi-thread processor adds for each stage of production line a prediction circuit for an effective thread instruction and a set of two-dimensional thread identity registers.