Opposite-Facing I/O Cell Columns for Shorter Wiring and Latch-Up Spacing
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Solution Overview
Problem
The increasing scale of semiconductor integrated circuits with multiple input and output signals leads to area limitations due to longer signal lines and potential latch-up errors caused by voltage differences between higher and lower power supply regions, necessitating increased distances between transistors and wells, which in turn increases the device area.
Innovation Solution
The semiconductor integrated circuit device is configured with 2×N IO cell columns, where N is an integer of two or more, with each column aligned perpendicular to the chip periphery, allowing the lower power supply voltage region to face either the core region or other lower power supply regions, reducing the need for space to avoid latch-up errors and minimizing wiring delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If IO cells are arranged in one column around the core region, then the device area is reduced, but the signal line length increases causing larger delays
Solution Approach 1:
The patent transitions from a single-column arrangement to a two-column arrangement of IO cells, utilizing two-dimensional spatial distribution. This dimensional change allows IO cells to be positioned closer to the core region while maintaining compact device area, thereby reducing signal line lengths and associated delays.
2Reliability
If the distance between higher and lower power supply voltage regions is increased to avoid latch-up errors, then reliability is improved, but the device area increases
Solution Approach 1:
The patent segments the IO cell columns into two distinct groups: a first column group with higher power supply voltage regions facing the core region, and a second column group with lower power supply voltage regions facing the core region. This segmentation allows adjacent columns with different voltage levels to face each other, eliminating the need for large spacing and reducing device area while maintaining reliability.
Solution Approach 2:
Instead of placing higher and lower power supply voltage regions in alternating sequence (which would require large spacing), the patent inverts the conventional approach by having columns with the same voltage level face each other. This inversion allows adjacent columns to have different voltage levels, reducing the required distance and device area.
3Area of stationary object
If IO cells are placed closer to the periphery to reduce area, then device area is reduced, but signal line length and delays increase
Solution Approach 1:
The patent utilizes a two-column configuration that distributes IO cells across different spatial positions, allowing them to be closer to the core region without increasing device area. This two-dimensional arrangement reduces signal line lengths and associated time delays compared to single-column peripheral arrangements.
Data Source
AI summary
Provided is a semiconductor integrated circuit device including a plurality of columns of IO cells and having a configuration capable of reducing wiring delays without causing an increase in the area. The semiconductor integrated circuit device includes a first IO cell column group including an IO cell column closest to a periphery of a chip, and a second IO cell column group including an IO cell column adjacent to the first IO cell column group at the side closer to the core region. At least one of the first IO cell column group or the second IO cell column group includes two or more IO cell columns, and the two or more IO cell columns are aligned in the second direction such that the lower power supply voltage regions face each other or the higher power supply voltage regions face each other.