Optical Semiconductor Electrode Layout for Solder-Stable Mounting

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Solution Overview

Problem

Light emitting and receiving elements face challenges in stable connection to external members via solder and in improving light emission/reception efficiency, with issues such as solder diffusion and potential short circuits.

Innovation Solution

The optical semiconductor element features a substrate with cells having distinct electrode areas, where the second electrode has a smaller area to prevent solder diffusion and a larger first electrode for efficient current distribution, along with a mesa structure and specific layer configurations to enhance stability and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the second electrode has a large area to improve current distribution, then light emission efficiency is improved, but solder diffusion into the electrode increases

Engineering Contradiction:
Improvelight emission efficiencyVSAvoidconnection stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by creating different electrode area configurations in different regions. The first electrode has a larger area for current distribution while the second electrode has a smaller area to prevent solder diffusion. This spatial differentiation of electrode properties resolves the contradiction between improving light emission efficiency and ensuring connection stability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the electrode structure into distinct first and second electrodes with different area characteristics. This segmentation allows each electrode to be optimized for its specific function - the first electrode for current distribution and the second electrode for solder connection stability - thereby resolving the technical contradiction.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the first electrode has a large area for current distribution, then light emission efficiency is improved, but the complexity of electrode configuration increases

Engineering Contradiction:
Improvelight emission efficiencyVSAvoidelectrode configuration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent employs asymmetry by designing the first and second electrodes with different area characteristics. The first electrode has a larger area optimized for current distribution while the second electrode has a smaller area. This asymmetric configuration improves light emission efficiency while maintaining manageable complexity through clear functional differentiation.

Inventive Principle:
Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables stable connection to external members using solder while improving light emission/reception efficiency by reducing solder diffusion and preventing short circuits, allowing for easier identification and mounting of components.

Implementation Method 1

an optical layer that is an active layer that generates light

Methodology Applied
Scientific EffectElectroluminescence: Electroluminescence

Implementation Method 2

an absorption layer that absorbs light

Methodology Applied
Scientific EffectOptical absorption: Absorption (EM radiation)

Data Source

PatentUS20240421175A1Optical semiconductor element
Publication Date: 2024.12.19 HAMAMATSU PHOTONICS KK
  • US20240421175A1 patent drawing
  • US20240421175A1 patent drawing
  • US20240421175A1 patent drawing

AI summary

An optical semiconductor element includes: a substrate; and a plurality of cells formed on the substrate, the plurality of cells including a first cell, a second cell, and a third cell. A first electrode electrically connected to a first semiconductor layer of the first cell is arranged on the top surface of the first cell, and a second electrode electrically connected to a second semiconductor layer of the third cell is arranged on the top surface of the second cell. Each of the first electrode and the second electrode has a planned contact region with which solder comes into contact during electrical connection with an external member. When viewed from the thickness direction of the substrate, the area of the second electrode on the top surface of the second cell is smaller than the area of the first electrode on the top surface of the first cell.