3D Optical Package Stacking Without TSV-Induced Thermal Stress
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Solution Overview
Problem
Existing packaging technologies for integrating photonic and electronic dies in 3D or 2.5D packages face reliability issues due to thermal stress from through semiconductor vias (TSVs) and high fabrication costs.
Innovation Solution
Implementing electronic dies with dual-sided interconnect structures that provide backside power delivery, allowing photonic dies to be stacked without TSVs, thereby eliminating the need for TSVs in both types of dies and reducing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through semiconductor vias (TSVs) are used to connect stacked chips/dies, then electrical and physical connections are established, but reliability deteriorates due to thermal stress and fabrication costs increase
Solution Approach 1:
The patent removes TSVs from the photonic die by implementing backside power delivery through the electronic die. Power and signal delivery functions are extracted from the photonic die and relocated to the electronic die's backside interconnect structures, eliminating the need for TSVs in the photonic die and reducing thermal stress and fabrication complexity.
Solution Approach 2:
The patent transitions from vertical through-die connections (TSVs) to backside interconnect structures on the electronic die. By utilizing the backside of the electronic die for power and signal delivery, the invention eliminates the need for vertical vias through the photonic die, reducing structural complexity and thermal stress while maintaining 3D stacking benefits.
2Ease of manufacture
If TSVs are implemented in photonic dies, then power delivery is achieved, but fabrication costs increase and manufacturing complexity increases
Solution Approach 1:
The electronic die's backside interconnect structures are designed to perform multiple functions: power delivery to the photonic die, signal routing, and electrical connection to the package substrate. This multi-functional approach eliminates the need for separate TSV structures in the photonic die, simplifying fabrication and reducing overall packaging complexity.
Solution Approach 2:
The patent merges the power delivery function with the backside interconnect structures of the electronic die. Instead of implementing separate power delivery mechanisms through TSVs in the photonic die, the invention combines power and signal delivery functions into the electronic die's existing backside interconnect infrastructure, reducing manufacturing steps and complexity.
3Reliability
If photonic dies are stacked on electronic dies using TSVs, then integration is achieved, but thermal stress increases causing reliability issues
Solution Approach 1:
The patent extracts the power and signal delivery function from the photonic die's TSV structures and relocates it to the electronic die's backside interconnect structures. This elimination of TSVs in the photonic die removes a major source of thermal stress, as TSVs are prone to thermal expansion mismatches between different materials, thereby improving package reliability.
Data Source
AI summary
An exemplary package includes a photonic die, an electronic die, and a package component. The electronic die has an electronic device layer disposed between a frontside interconnect structure and a backside interconnect structure. The backside interconnect structure is configured to deliver power to the electronic device layer. The photonic die, the electronic die, and the package component are stacked top-to-bottom. The backside interconnect structure of the electronic die is connected to the package component, and the photonic die is connected to the electronic die. In some embodiments, the photonic die and the electronic die are each free of through semiconductor vias, such as through silicon vias. In some embodiments, a frontside interconnect structure of the photonic die is connected to the frontside interconnect structure of the electronic die. In some embodiments, a backside interconnect structure of the photonic die is connected to the frontside interconnect structure of the electronic die.