Optical Receiver Threshold Compensation for Asymmetrical Noise
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Solution Overview
Problem
Optical noise asymmetry in optical fiber datalinks results in higher bit error rates for differential '1' bits compared to '0' bits due to uneven eye heights after optical-to-electrical conversion, necessitating adjustment of zero-crossing points to balance these eye heights.
Innovation Solution
The implementation of a threshold adjustment circuit using two voltage-mode digital-to-analog converter (DAC) circuits at the optical receiver front end, which adjusts the zero-crossing points of positive and negative data signals by generating adjustment signals to pull up the zero-crossing point of positive data and pull down the zero-crossing point of negative data, while reducing power consumption through the use of high-value resistances and AC coupling capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional optical-to-electrical conversion is used without threshold adjustment, then the circuit structure is simple, but the bit error rate is high due to asymmetrical optical noise causing unbalanced eye heights
Solution Approach 1:
The threshold adjustment function is segmented into two independent DAC circuits, each handling one differential signal line. This segmentation allows independent optimization of each line's threshold while maintaining overall system manageability and reducing the complexity burden compared to a unified adjustment mechanism.
Solution Approach 2:
The DAC circuits perform preliminary threshold adjustment on the differential signals before they enter the equalizer. By pre-adjusting the zero-crossing points and balancing the eye heights in advance, the equalizer can operate more effectively, improving overall system reliability without requiring complex real-time adjustments.
2Reliability
If threshold adjustment circuitry is added to balance eye heights, then the bit error rate decreases, but the power consumption increases
Solution Approach 1:
The invention uses high-value resistors in the DAC circuits to change the electrical parameters of the threshold adjustment mechanism. By increasing the resistance values, the current consumption is reduced while still achieving the necessary threshold adjustment range, thus lowering power consumption while maintaining bit error rate improvement.
Solution Approach 2:
The threshold adjustment is implemented through periodic calibration sequences rather than continuous adjustment. During normal data transmission, the thresholds remain fixed at calibrated values, consuming minimal power. The DAC circuits are activated periodically for recalibration, reducing average power consumption compared to continuous adjustment schemes.
3Loss of energy
If high-value resistances are used in DAC circuits to reduce power consumption, then current dissipation decreases, but the adjustment signal strength may be weakened
Solution Approach 1:
The two DAC circuits are configured with asymmetric resistor values optimized for their respective differential signal lines. Each DAC can use different resistance values tailored to its specific signal characteristics, allowing one to compensate for the high-value resistor power savings while maintaining adequate signal strength where needed.
Solution Approach 2:
The system incorporates feedback mechanisms that monitor the effectiveness of threshold adjustment and automatically adjust DAC control codes to optimize the balance between signal strength and power consumption. The feedback loop ensures that high-value resistors do not overly weaken adjustment signals by dynamically compensating through control signal modulation.
Data Source
AI summary
An optical data circuit includes threshold adjustment circuits to perform threshold adjustment compensation of asymmetrical optical noise. The optical data circuit includes an optical-to-electrical conversion circuit configured to produce first and second differential electrical data signals, at respective first and second electrical nodes, in response to an optical data signal. First and second digital-to-analog converter (DAC) circuits are each respectively coupled to the first and second electrical nodes and configured to respectively generate first and second adjustment signals. The first and second DAC circuits are configured to adjust the first and second differential electrical data signals such that a zero-crossing point of positive data is pulled up in response to the first adjustment signal and a zero-crossing point of negative data is pulled down in response to the second adjustment signal.