Optimized Latch Clock Design for Faster SRAM Write Cycles
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Solution Overview
Problem
The performance of pseudo-dual/port SRAM is limited by the longer time required for read and write operations in the same clock cycle, with the write operation often being the bottleneck, due to the clock cycle time needing to accommodate the slower of the two operations.
Innovation Solution
The implementation of a clock generation scheme that includes multiple latch circuits with overlapping clock signals, allowing read and write operations to be performed within the same clock cycle by using first and second edges of an internal clock signal, with each latch circuit generating subsequent output signals based on specific latch clock signals, and a gating circuit to generate a write signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single clock signal is used for both read and write operations in pseudo-dual-port 6T SRAM, then the clock cycle time must be long enough to accommodate the slower operation (write), but this limits the maximum operating frequency and overall performance
Solution Approach 1:
The patent segments the clock signaling into separate paths: a first clock signal controls read operations while a second clock signal controls write operations. This segmentation allows each operation type to be optimized independently, enabling the write operation to complete faster without constraining the read operation timing, thereby increasing the maximum operating frequency
Solution Approach 2:
The patent introduces dynamic clocking where the clock signals for read and write operations can have different frequencies and phases. The write clock signal is specifically optimized to complete write operations faster, while the read clock signal maintains appropriate timing for read operations. This dynamic approach allows the system to operate at higher frequencies by adapting clock timing to operational requirements
2Reliability
If the clock cycle time is extended to accommodate the slower write operation, then write operations can complete successfully, but the overall system throughput and performance are reduced
Solution Approach 1:
By segmenting the clock control into separate signals for read and write operations, the patent enables write operations to complete in a shorter time window without forcing the entire clock cycle to extend. This segmentation ensures write operation reliability while maintaining shorter cycle times for higher throughput
Solution Approach 2:
The patent changes the timing parameters of the clock signals, specifically optimizing the write clock signal to have a shorter duration or different phase relationship with the data signals. This parameter optimization allows write operations to complete reliably faster, increasing system throughput without sacrificing write operation success rate
Data Source
AI summary
A memory device is provided and includes a memory array, first to second latch circuits and a gating circuit. Read and write operations are triggered by first and second edges of an internal clock signal respectively. The first latch circuit generates a first output signal in response to an input signal and a first latch clock signal, a first edge of the first latch clock signal generated based on the first edge of the internal clock signal. The second latch circuit generates a second output signal in response to the first output signal and a second latch clock signal, a first edge of the second latch clock signal being between first and second edges of the first latch clock signal. The gating circuit generates, in response to the second output signal and a gating clock generated, a third output signal to the memory array.