Optoelectronic Semiconductor Chip Insulation and Contact Segmentation

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Solution Overview

Problem

Existing optoelectronic semiconductor chips face challenges in maintaining stability over time due to defects in electrical insulation, which can lead to electrical short circuits and current leaks, and require complex contact-connection methods during manufacturing.

Innovation Solution

The design features an optoelectronic semiconductor chip with an electrically insulating carrier and structured conductive contact layers, including p-side and n-side contact regions, insulation regions, and spacer layers to ensure defect-free electrical insulation and mechanical fixation of the optoelectronic structure, eliminating the need for complex contact-connection methods within the chip itself.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complex contact-connection methods are used within the chip, then electrical connection reliability is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidcontact-connection complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The contact layer is segmented into distinct p-side contact regions and n-side contact regions that are spatially separated and electrically insulated from each other. This segmentation allows for simplified individual connections while maintaining overall electrical connection reliability through the structured arrangement of contact regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An electrically insulating spacer layer is introduced as an intermediary element between the contact layer and the optoelectronic structure. This spacer layer provides both electrical insulation and mechanical support, eliminating the need for complex contact-connection methods while ensuring reliable electrical connections through the structured contact regions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If insulation regions are added to prevent electrical short circuits, then electrical insulation reliability is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical insulation reliabilityVSAvoidinsulation structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The electrically insulating spacer layer combines multiple functions into a single element: it provides electrical insulation between conductive layers, serves as a mechanical support structure, and defines the spatial arrangement of contact regions. This merging reduces the number of separate insulation components needed while maintaining high electrical insulation reliability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The spacer layer is designed as a multi-functional element that simultaneously provides electrical insulation, mechanical support, and structural definition for the contact regions. This universal element eliminates the need for separate insulation structures, reducing device complexity while ensuring defect-free electrical insulation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If the carrier provides mechanical fixation, then manufacturing complexity is reduced, but the need for additional auxiliary carriers increases device complexity

Engineering Contradiction:
Improvemanufacturing complexityVSAvoidcarrier structure complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The carrier is pre-designed with integrated mechanical fixation structures and electrically insulating properties before the manufacturing process begins. This preliminary design of the carrier with built-in fixation capabilities eliminates the need for additional auxiliary carriers, reducing device complexity while maintaining ease of manufacture.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9343642B2Optoelectronic semiconductor chip
Publication Date: 2016.05.17 OSRAM OLED
  • US9343642B2 patent drawing
  • US9343642B2 patent drawing
  • US9343642B2 patent drawing

AI summary

An optoelectronic semiconductor chip includes a carrier including a carrier element having a mounting side; one electrically conductive n-type wiring layer arranged at the mounting side; a structured, electrically conductive contact layer having a p-side and n-side contact region and arranged at a side of the n-type wiring layer facing away from the carrier element; at least one insulation region electrically insulating the p-side contact region from the n-side contact region; at least one electrically insulating spacer layer arranged at a side of the n-type wiring layer facing away from the carrier element in a vertical direction between the p-side contact region and the n-type wiring layer, wherein the n-side contact region and the n-type wiring layer electrically conductively connect to one another, and the p-side contact region and the spacer layer border the n-side contact region in a lateral direction; an optoelectronic structure connected to the carrier.