Optoelectronic Semiconductor Chip with Self-Aligning Mirror Protection
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Solution Overview
Problem
Existing methods for producing optoelectronic semiconductor chips often result in a significant portion of the active area being shaded or absorbed by metallic current spreading webs and electrical contact points, limiting the chip's efficiency and requiring complex and costly production steps.
Innovation Solution
A method involving the deposition of a semiconductor layer sequence on a growth substrate, followed by the arrangement of a metallic mirror layer and a self-aligning mirror protection layer, which allows for partial removal of the semiconductor layer sequence without exposing the growth substrate, thereby reducing the need for additional contact points and enhancing the active area's usability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If metallic current spreading webs and electrical contact points are used on the top side of the semiconductor chip, then electrical connection is achieved, but the active area is shaded and absorbed, reducing the usable area for electromagnetic radiation
Solution Approach 1:
The invention extracts the electrical contact function from the top side of the semiconductor chip by removing metallic current spreading webs and bond pads from the radiation-receiving surface. Electrical connections are established exclusively through the carrier substrate, allowing the entire top surface to remain free for electromagnetic radiation reception without shading or absorption by metal contacts
Solution Approach 2:
The invention moves the electrical contact function to another dimension by implementing all electrical connections through the carrier substrate (bottom side) rather than the top radiation-receiving surface. This dimensional shift allows complete clearance of the top surface for optical functionality while maintaining all necessary electrical pathways through the substrate structure
2Ease of manufacture
If polishing and metal web production steps are implemented to create contact points, then electrical connection is established, but the production process becomes complex and time-consuming
Solution Approach 1:
The invention extracts and eliminates complex production steps such as polishing the top side and producing metal webs for current spreading. By designing the chip structure to require no top-side contact points, these cumbersome manufacturing operations become unnecessary, streamlining the production process
Solution Approach 2:
The invention applies preliminary action by pre-structuring the semiconductor layer sequence and carrier substrate during initial fabrication to enable bottom-side-only contact. The carrier substrate is designed with integrated contact structures and the semiconductor layers are configured during growth to allow direct electrical connection through the substrate, eliminating the need for subsequent complex contact formation steps
3Ease of manufacture
If electrical contact points are placed on the top side, then current injection is achieved, but additional protective layers and insulating structures are required, increasing device complexity
Solution Approach 1:
The invention extracts the electrical contact function entirely from the top side, eliminating the need for protective layers, insulating structures, and Schottky barriers that would otherwise be required to protect and isolate top-side contact points. The carrier substrate itself serves as the protective and insulating structure
Solution Approach 2:
The carrier substrate is designed to perform multiple functions simultaneously: it provides mechanical support, establishes electrical connections, and serves as the insulating structure between different contact regions. This multi-functionality eliminates the need for separate protective and insulating layers that would increase device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method increases the usable area of the optoelectronic semiconductor chip, reduces transition resistance, and enhances electrical efficiency while minimizing material damage and contaminants, making the process more cost-effective and time-efficient.
Implementation Method 1
subsequently a metallic mirror layer is arranged on a top side of the semiconductor layer sequence facing away from the growth substrate
Implementation Method 2
The semiconductor layer sequence is epitactically deposited on a growth substrate, for example
Data Source
AI summary
A method for producing an optoelectronic semiconductor chip is disclosed. In some embodiment the method includes arranging a metallic mirror layer on a top side of a semiconductor layer sequence, arranging a mirror protection layer at least on exposed lateral surfaces of the mirror layer in a self-aligning manner, wherein the mirror layer has openings toward the semiconductor layer sequence, and wherein the openings are framed in lateral directions by the mirror protection layer and partially removing the semiconductor layer sequence in a region of the openings of the mirror layer.