Optoelectronic Semiconductor Component With Molded Carrier ESD Protection
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Solution Overview
Problem
Optoelectronic semiconductor devices are prone to short circuits and electrostatic discharges (ESD), and existing production methods are complex, making them sensitive to these issues.
Innovation Solution
An optoelectronic semiconductor device with a semiconductor body and a plastics carrier produced using molding methods, featuring through-vias for electrical contacting, a p-connection layer, an n-connection layer, and an ESD protective element with direction-dependent conductivity to mitigate short circuits and ESD, while being surface-mountable and radiation-efficient.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional production methods are used for optoelectronic semiconductor devices, then manufacturing capability is maintained, but the devices are highly sensitive to short circuits and electrostatic discharges (ESD) and production complexity increases
Solution Approach 1:
The patent introduces a molded carrier as an intermediary component between the semiconductor body and the mounting substrate. This carrier integrates multiple functions: it provides mechanical support, establishes electrical connections through molded-through holes, and incorporates ESD protection elements. By consolidating these functions into a single molded component, the system reduces sensitivity to short circuits and ESD while avoiding the need for complex separate assembly steps.
Solution Approach 2:
The patent merges multiple previously separate components and functions into a single molded carrier structure. The carrier integrates electrical connection elements, ESD protection elements, and mechanical support functions into one unified component produced through mold injection. This consolidation simplifies production by reducing the number of discrete parts and assembly operations while simultaneously improving reliability through integrated ESD protection.
2Ease of manufacture
If connection layers are placed on the radiation exit face for electrical contacting, then electrical connectivity is achieved, but radiant yield decreases due to absorption and scattering of light
Solution Approach 1:
The patent moves the electrical connection interface from the radiation exit face (2D surface) to the opposite side of the device. The molded carrier establishes electrical connections through molded-through holes that pass through the carrier body, allowing p-type and n-type connection layers to be positioned on the mounting surface rather than the radiation exit face. This spatial reconfiguration maintains electrical connectivity while eliminating the interference of connection layers with light emission.
Solution Approach 2:
The patent segments the device into distinct functional zones: the radiation exit face is dedicated solely to light emission without any connection layers, while electrical connections are established through separate molded-through holes in the carrier. This segmentation allows the radiation exit face to remain optically clean for maximum radiant yield, while electrical connectivity is achieved through the segmented connection structure in the carrier.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces sensitivity to short circuits and ESD, simplifies production, and enhances radiant yield by isolating connection layers from the radiation exit face, ensuring effective electrical connectivity and protection against high voltages.
Implementation Method 1
an ESD protective element with direction-dependent conductivity to mitigate short circuits and ESD
Implementation Method 2
The active layer may in particular be a radiation-emitting active layer
Data Source
AI summary
An optoelectronic semiconductor component is disclosed, comprising: a semiconductor body (1) having a semiconductor layer sequence (2) with a p-type semiconductor region (3), an n-type semiconductor region (5), and an active layer (4) arranged between the p-type semiconductor region (3) and the n-type semiconductor region (5); a support (10) having a plastic material and a first via (11) and a second via (12); a p-contact layer (7) and an n-contact layer (8), at least some regions of which are arranged between the support (10) and the semiconductor body (1), wherein the p-contact layer (7) connects the first via (11) to the p-type semiconductor region (3) and the n-contact layer (8, 8A) connects the second via (12) to the n-type semiconductor region (5); and an ESD protection element (15) which is arranged between the support (10) and the semiconductor body (1), wherein the ESD protection element (15) is electrically conductively connected to the first via (11) and to the second via (12), and wherein a forward direction of the ESD protection element (15) is anti-parallel to a forward direction of the semiconductor layer sequence (2).