Organic TFT Gate Insulator Segmentation for Fine Through Holes
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Solution Overview
Problem
Existing methods for forming through holes in gate insulating layers of organic thin film transistors are complex and costly, and often result in poor insulation properties and limited pattern precision, making it difficult to connect electrodes effectively.
Innovation Solution
A manufacturing method involving a non-photosensitive resin layer as the first gate insulating layer and a photosensitive resin layer as the second gate insulating layer, with a through hole formed in the photosensitive resin layer, allowing for improved electrical characteristics and fine pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a lithography method is used to form through holes in the gate insulating layer, then electrical connection between layers can be achieved, but the manufacturing process becomes complicated and costly
Solution Approach 1:
The gate insulating layer is divided into two separate layers: a lower gate insulating layer and an upper gate insulating layer. This segmentation allows the through hole to be formed only in the upper layer, simplifying the manufacturing process while maintaining proper electrical connection. The lower layer remains intact to provide continuous insulation and support the gate electrode structure.
Solution Approach 2:
The upper gate insulating layer is selectively removed only in the region where the through hole is needed, while the lower gate insulating layer remains intact elsewhere. This local quality approach enables precise interlayer connection without compromising the overall insulating properties of the gate structure, and avoids the need for complex lithography processes.
2Manufacturing precision
If RIE processing is used with gate electrode as mask, then through hole formation is achieved, but additional electrode layers are required for connection
Solution Approach 1:
The upper gate insulating layer is extracted or removed only in the specific region where the through hole is required. This selective removal creates the interlayer connection opening without requiring additional electrode layers for masking, as the upper insulating layer itself serves as the mask during the formation process.
3Device complexity
If the gate electrode edge is common with gate insulating layer pattern edge, then structure is simplified, but insulating properties between gate and source/drain electrodes deteriorate
Solution Approach 1:
The gate insulating layer is segmented into two layers with the lower layer extending beyond the gate electrode edge. This segmentation creates an insulating barrier between the gate electrode and source/drain electrodes, preventing direct contact and maintaining proper electrical isolation while keeping the overall structure relatively simple.
Solution Approach 2:
The insulating structure is extended into the vertical dimension by having the lower gate insulating layer protrude beyond the gate electrode edge in the lateral direction. This dimensional approach provides effective electrical isolation without requiring additional lateral spacing or complex planar structures.
4Ease of manufacture
If solvent is supplied by needle to dissolve insulating layer, then connection can be made, but fine openings cannot be formed
Solution Approach 1:
The gate insulating layer is segmented into two layers with different thicknesses and removal characteristics. The upper layer is thinner and designed to be selectively removed to form fine through holes, while the lower layer provides structural support and continuous insulation. This segmentation enables the formation of precise fine openings that would be difficult to achieve with needle-based solvent methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the electrical performance of thin film transistors by reducing contact resistance and improving interface characteristics, enabling high-current driving capability and efficient interlayer connections while maintaining low manufacturing costs.
Implementation Method 1
forming a photosensitive resin layer as the second gate insulating layer on the first gate insulating layer, and forming a through hole in the photosensitive resin layer
Data Source
AI summary
According to one embodiment, there is provided a manufacturing method of an electronic device including a lower electrode, a source electrode and a drain electrode made of a nanoparticulate conductive material on a substrate, an organic semiconductor layer between the source and drain electrodes, and a gate electrode on the organic semiconductor layer via a gate insulating layer. The manufacturing method includes forming a nonphotosensitive resin layer as the gate insulating layer on the organic semiconductor layer and on the lower electrode, forming a photosensitive resin layer as the gate insulating layer on the nonphotosensitive resin layer, and forming a through hole in the photosensitive resin layer on the lower electrode.