Organic Thin-Film Transistor Sacrificial Layer Residue Removal
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Solution Overview
Problem
Conventional organic thin-film transistors suffer from deteriorated characteristics due to residues from the patterning of partition wall parts, which hinder crystallization and increase contact resistances between the source and drain electrodes and the organic semiconductor layer.
Innovation Solution
A method involving the formation of a sacrificial layer above the source and drain electrodes, with a partition wall layer that exposes the gate insulator and a portion of the sacrificial layer, allowing for the removal of residues and ensuring the source and drain electrodes occupy 50% or more of the opening surface, with a spacing smaller than the average crystal diameter, facilitating better crystallization and reduced contact resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a partition wall part is formed by conventional patterning methods, then the transistor structure is defined, but residues remain on the source and drain electrodes which deteriorate TFT characteristics
Solution Approach 1:
The partition wall structure is segmented into two functional parts: an upper partition wall layer that defines the pattern, and a lower sacrificial layer that is removed to eliminate residues. This segmentation allows the pattern-defining function to be separated from the residue-removal function, solving the contradiction between precise patterning and residue elimination.
Solution Approach 2:
The sacrificial layer acts as an intermediary element between the source and drain electrodes. It is temporarily introduced to support the upper partition wall layer during patterning, then removed to clean the electrode surfaces. This intermediary approach enables precise pattern definition while eliminating harmful residues that would otherwise remain on the electrodes.
2Ease of manufacture
If the source and drain electrodes are spaced apart conventionally, then fabrication is simplified, but contact resistances increase and crystallization is hindered
Solution Approach 1:
The spacing between source and drain electrodes is optimized to a specific range (0.5-2.0 μm) that balances fabrication ease with electrical performance. Additionally, the exposed area ratio of the electrodes is controlled to be 30-70%, which optimizes both the crystallization process and contact resistance. These parameter changes enable improved reliability while maintaining ease of manufacture.
Solution Approach 2:
The electrode spacing and exposed area are locally optimized in the channel formation region. By controlling the local geometry of the electrodes where they interface with the organic semiconductor layer, the invention improves crystallization and reduces contact resistance specifically at the critical contact points, while the overall structure remains simple to fabricate.
3Stability of the object's composition
If the organic semiconductor layer is formed with small electrode exposure, then coverage is improved, but crystallization is hindered and contact resistances increase
Solution Approach 1:
The exposed area ratio of the source and drain electrodes is optimized to a specific range (30-70%). This parameter optimization ensures sufficient electrode exposure to promote crystal growth and reduce contact resistance, while maintaining adequate coverage for stable layer composition. The dual-parameter control (exposed area ratio and spacing) resolves the contradiction between coverage and crystallization quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in organic thin-film transistors with improved TFT characteristics, including enhanced ON characteristics and increased carrier mobility by promoting large crystal growth and reducing grain boundaries.
Implementation Method 1
promoting large crystal growth and reducing grain boundaries
Data Source
AI summary
A transistor manufacturing method includes: forming a gate electrode above a substrate; forming a gate insulator above the gate electrode; forming source and drain electrodes above the gate insulator; forming a sacrificial layer above the source and drain electrodes; forming a partition wall layer above the sacrificial layer; forming an opening by patterning the partition wall layer to partly expose the sacrificial layer; removing the sacrificial layer to expose the source and drain electrodes; and forming an organic semiconductor layer to cover the source and drain electrodes and the gate insulator, wherein the source and drain electrodes occupy 50% or more of a surface area of the opening, and the source and drain electrodes are spaced apart at an interval smaller than an average granular diameter of crystals each of which is at least partly positioned above the source or drain electrode.