Organic Transistor Non-Uniform Semiconductor Layer Thickness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in organic transistors is controlling the thickness of the semiconductor layer to achieve satisfactory electrical characteristics, as a large channel region thickness improves performance, but is difficult to maintain due to increased on-resistance and trap numbers, especially when using organic semiconductors.
Innovation Solution
The organic transistor design includes a semiconductor layer with distinct thickness portions where the channel region has a larger thickness, while the portions connected to the source and drain electrodes have smaller thicknesses, achieved through specific ink jet method and drying conditions to form a rising middle portion with controlled thickness profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel region thickness is increased to improve electrical characteristics, then mobility and on/off ratio are improved, but on-resistance increases and manufacturing precision becomes difficult to control
Solution Approach 1:
The patent applies local quality by creating a semiconductor layer with non-uniform thickness distribution. The channel region (central portion) has a larger thickness (W3) to improve electrical characteristics, while the source and drain regions (first and second portions) have smaller thicknesses (W1 and W2) to reduce on-resistance. This localized thickness variation resolves the contradiction by optimizing each region's thickness for its specific functional requirements.
Solution Approach 2:
The patent segments the semiconductor layer into three distinct portions: a first portion (source region), a second portion (drain region), and a central portion (channel region). Each portion has different thickness characteristics (W1 < W3, W2 < W3) and serves different functional purposes. This segmentation allows independent optimization of each region's thickness to simultaneously achieve low on-resistance and high mobility.
2Reliability
If the semiconductor layer thickness is made large to improve channel characteristics, then carrier mobility increases, but the number of traps increases and on-resistance increases
Solution Approach 1:
The patent applies local quality by creating a semiconductor layer with non-uniform thickness distribution. The channel region (central portion) has a larger thickness (W3) to improve electrical characteristics, while the source and drain regions (first and second portions) have smaller thicknesses (W1 and W2) to reduce on-resistance. This localized thickness variation resolves the contradiction by optimizing each region's thickness for its specific functional requirements.
Solution Approach 2:
The patent changes the thickness parameter of the semiconductor layer across different regions. By varying the thickness from small (W1, W2) in source/drain regions to large (W3) in the channel region, the patent optimizes carrier mobility in the channel while minimizing on-resistance in the source and drain regions, thus resolving the contradiction between mobility improvement and trap reduction.
3Ease of manufacture
If a uniform thickness semiconductor layer is used for simple manufacturing, then ease of manufacture is improved, but electrical characteristics become difficult to control
Solution Approach 1:
The patent applies local quality by creating a semiconductor layer with non-uniform thickness distribution. The channel region (central portion) has a larger thickness (W3) to improve electrical characteristics, while the source and drain regions (first and second portions) have smaller thicknesses (W1 and W2) to reduce on-resistance. This localized thickness variation resolves the contradiction by optimizing each region's thickness for its specific functional requirements.
Solution Approach 2:
The patent introduces dynamic variation in the semiconductor layer thickness rather than using a static uniform thickness. The thickness dynamically changes across the layer, being smaller (W1, W2) in source/drain regions and larger (W3) in the channel region. This dynamic thickness profile enables simultaneous optimization of manufacturing simplicity and electrical characteristics control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances mobility, on/off ratio, threshold voltage, and reduces dispersion, resulting in superior electrical characteristics and reduced parasitic capacitance.
Implementation Method 1
achieved through specific ink jet method and drying conditions to form a rising middle portion with controlled thickness profiles
Data Source
AI summary
An organic transistor includes a source electrode and a drain electrode, and an organic semiconductor layer disposed across between the source electrode and the drain electrode. The organic semiconductor layer includes a first semiconductor portion in a region where a gate electrode and the source electrode oppose each other, a second semiconductor portion in a region where the gate electrode and the drain electrode oppose each other, and a third semiconductor portion between the first semiconductor portion and the second semiconductor portion. The first semiconductor portion, the second semiconductor portion, and the third semiconductor portion satisfy the relationships W1<W3 and W2<W3, wherein W1 represents the average thickness of the first semiconductor portion, W2 represents the average thickness of the second semiconductor portion, and W3 represents the average thickness of the third semiconductor portion.