Orthogonal Die Stack Architecture for Power and Heat Limits
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Solution Overview
Problem
Conventional IC die stacking architectures are limited by power and heat removal constraints, particularly when high-power compute IC dies are placed on top, limiting the number of dies that can be stacked due to inefficient power delivery and heat dissipation.
Innovation Solution
The die stack is positioned orthogonal to the base, allowing direct power delivery and input/output communication to each die, with each die connected directly to the base without routing through other dies, and incorporating a spacer layer for thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If dies are stacked in conventional parallel architecture, then mechanical stability is achieved, but power delivery efficiency deteriorates and heat removal becomes inefficient
Solution Approach 1:
The patent transitions from conventional parallel die stacking (2D arrangement) to an orthogonal 3D configuration where dies are stacked perpendicular to the base substrate. This dimensional change enables direct vertical power delivery paths and improved thermal management, resolving the contradiction between mechanical stability and power delivery efficiency.
Solution Approach 2:
The patent divides the power delivery and thermal management functions into separate dedicated structures: power delivery through vertical conductive interconnects and heat removal through independent thermal vias and heat sinks. This segmentation allows each function to be optimized independently, improving overall system performance.
2Productivity
If more high-power compute IC dies are stacked, then computing performance is improved, but heat dissipation becomes insufficient
Solution Approach 1:
The patent introduces thermal vias and heat sink structures as intermediary elements between the stacked dies and the external environment. These intermediaries provide dedicated thermal pathways that efficiently conduct heat away from high-power compute dies, enabling higher computing performance without thermal runaway.
Solution Approach 2:
The patent implements localized thermal management by placing thermal vias and heat dissipation structures specifically at high-heat-generation regions of the stacked dies. This local quality approach optimizes heat removal efficiency where it is most needed, supporting higher computing performance.
3Ease of operation
If dies are connected through other dies in the stack, then I/O communication is achieved, but signal transmission efficiency deteriorates
Solution Approach 1:
The patent implements direct vertical I/O communication paths that connect dies to the base substrate without requiring signals to route through intermediate dies. This dimensional reconfiguration of signal paths eliminates unnecessary transmission hops, improving signal transmission efficiency and speed.
4Adaptability or versatility
If the number of stacked dies is increased, then device functionality is improved, but the architecture complexity increases
Solution Approach 1:
The patent employs universal orthogonal stacking architecture that can accommodate multiple die types (compute dies, memory dies, I/O dies) in a standardized configuration. This multi-functional design allows the same basic architecture to support diverse device functionalities without proportionally increasing complexity, as each die type follows the same connection and mounting paradigm.
Data Source
AI summary
Microelectronic assemblies with a die stack positioned such that a face of each die in the stack is orthogonal to a face of a base are disclosed. Each die has a first face and a second face opposite the first face. The die stack includes multiple dies, with the faces of each die parallel to the faces of the other dies in the die stack. The die stack is positioned on the base such that the faces of each die are substantially orthogonal to the face of the base. Each die in the die stack can have a corresponding conductive contact, and the conductive contact on each die in the die stack can be coupled to a conductive contact on the base via an interconnect. The interconnect can be a solder joint, such as a solder bump or solder ball.