Orthogonal DRAM Subarrays for Low-Power, Low-Latency Reads
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Solution Overview
Problem
Conventional DRAMs with bank structures face high power consumption and latency issues due to precharge or charge sharing operations during read operations, which are detrimental to battery-operated devices and overall performance.
Innovation Solution
Implementing orthogonal subarrays in DRAMs with localized dense connectivity between compute elements and memory portions, allowing direct access to local memory without a centralized memory controller, and utilizing orthogonal subarrays for tag-based lookup and matrix operations to minimize unnecessary charge sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If precharge or charge sharing operations are performed during read operations in conventional DRAM, then data can be read from memory banks, but power consumption increases and latency is extended
Solution Approach 1:
The memory bank is divided into multiple subarrays with different orientations (e.g., first subarray with bitlines in first direction, second subarray with bitlines in second direction). This segmentation allows selective access to only the required subarray, avoiding the need to precharge the entire bank or perform charge sharing operations across multiple subarrays, thereby reducing power consumption during read operations.
Solution Approach 2:
Each subarray is configured with specific orientation and can be independently accessed. The local quality of each subarray (its orientation and独立性) enables targeted read operations without affecting other subarrays, eliminating the need for blanket precharge operations across the whole bank and reducing overall power consumption.
2Reliability
If precharge or charge sharing operations are performed during read operations in conventional DRAM, then data can be read from memory banks, but read latency increases
Solution Approach 1:
By segmenting the bank into independently accessible subarrays with different orientations, the system can directly access the specific subarray containing the required data without waiting for precharge or charge sharing operations to complete across the entire bank, thereby reducing read latency.
Solution Approach 2:
The orthogonal subarrays are pre-configured with different orientations during memory design, enabling direct access to the required subarray based on the address pattern. This preliminary configuration eliminates the need for runtime precharge or charge sharing operations, reducing read latency.
3Device complexity
If centralized memory controller is used for memory access, then memory management is simplified, but access speed to local memory portions decreases
Solution Approach 1:
The memory system is segmented into multiple independently accessible subarrays with different orientations. This segmentation enables parallel or selective access to local memory portions without requiring centralized control for every access operation, improving access speed while maintaining manageable complexity through the structured subarray organization.
Solution Approach 2:
The patent introduces orthogonal orientations (different dimensions) for subarrays within the memory bank. This dimensional diversification allows simultaneous or selective access to different subarrays along different orientations, increasing access speed to local memory portions while the overall bank structure remains manageable.
Data Source
AI summary
In one embodiment, a memory comprises: a first subarray having a first plurality of memory cells, the first subarray having a first orientation; and a second subarray having a second plurality of memory cells, the second subarray having a second orientation, the second orientation orthogonal to the first orientation. Other embodiments are described and claimed.