Orthogonal Semiconductor Package with Conductive Pillars
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Solution Overview
Problem
Semiconductor packages face challenges in protecting electrical connections between chip pads from external damage and achieving high integration and reliability, particularly in preventing damage to these connections during subsequent processes.
Innovation Solution
A semiconductor package design featuring a lower semiconductor chip with chip pads on opposite sides, surrounded by conductive pillars and a molding element, with an upper semiconductor chip orthogonally stacked and connected via a redistribution pattern and insulating layers to external terminals, ensuring electrical connections are secure and reliable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chip pads are disposed close to opposite sides for high integration, then device density is improved, but electrical connections become more vulnerable to external damage
Solution Approach 1:
The patent transitions from planar electrical connections to three-dimensional vertical connections using conductive pillars. The chip pads are connected through vertically extending conductive pillars that pass through the molding compound, protecting the electrical connections from external damage while maintaining high integration density through orthogonal chip stacking.
Solution Approach 2:
The patent introduces conductive pillars as intermediary structures between chip pads and external terminals. These pillars serve as protective mediators that shield the electrical connections within the molding compound while establishing reliable electrical pathways from the chip pads to external connection points.
2Quantity of substance
If multiple chips are stacked vertically for high integration, then device capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor device into distinct functional segments: lower chip, upper chip, molding compound, conductive pillars, and insulating layers. Each segment performs a specific function and can be manufactured and assembled independently, simplifying the overall manufacturing process despite the three-dimensional structure.
Solution Approach 2:
The patent implements a nested structure where the lower chip is embedded in the molding compound, conductive pillars are formed within the molding compound, and the upper chip is stacked on top. This nested arrangement allows for systematic assembly and reduces manufacturing complexity by following a clear hierarchical construction sequence.
3Reliability
If conductive pillars surround the chip for protection, then electrical connection reliability is improved, but device volume increases
Solution Approach 1:
The patent uses a molding compound that forms a protective shell around the chip and conductive pillars. This shell provides mechanical protection and environmental sealing while maintaining a compact form factor. The molding compound acts as a thin-film encapsulation that protects internal structures without significantly increasing device volume.
Data Source
AI summary
According to example embodiments, a semiconductor package includes: a lower molding element; a lower semiconductor chip in the lower molding element and having lower chip pads on an upper surface and at an areas close to first and second sides of the lower molding element; conductive pillars surrounding the lower semiconductor chip and passing through the lower molding element; an upper semiconductor chip on the upper surface of the lower molding element and lower semiconductor chip, the upper semiconductor chip having upper chip pads on a top surface and at areas close to third and the fourth sides of the upper semiconductor chip, and a connecting structure on the lower molding element and the upper semiconductor chip and electrically connecting each of the lower chip pads and upper chip pads to a corresponding conductive pillar. The upper semiconductor chip is substantially orthogonal to the lower semiconductor chip.