Oscillator Bias Control for Accurate Clock Duty Ratio

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Solution Overview

Problem

Existing oscillation circuits struggle to accurately adjust the duty ratio of a clock signal due to nonlinear distortion in the waveform, making it difficult to achieve high accuracy in duty ratio adjustment.

Innovation Solution

A circuit device comprising an oscillation circuit, a waveform shaping circuit, and a duty adjustment circuit, where the duty adjustment circuit supplies a variably adjusted bias voltage to the oscillation circuit based on adjustment data to precisely control the duty ratio of the clock signal, independent of the reference voltage for temperature compensation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a bias circuit outputting a bias voltage about half of power supply voltage is provided to adjust duty ratio, then it is easy to adjust the duty ratio of output waveform to 50%, but high accuracy duty ratio adjustment cannot be achieved when nonlinear distortion occurs in the waveform itself

Engineering Contradiction:
Improveease of duty ratio adjustmentVSAvoidduty ratio accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent segments the duty ratio adjustment function into two independent parts: (1) a bias circuit that provides a bias voltage about half of the power supply voltage to enable easy duty ratio adjustment to 50%, and (2) a duty adjustment circuit that supplies an adjustment voltage to accurately correct the duty ratio when nonlinear distortion occurs. This segmentation allows each circuit to specialize in one aspect, resolving the contradiction between ease of operation and measurement precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a duty adjustment circuit as an intermediary component between the oscillation circuit and the output circuit. This intermediary circuit receives the oscillation signal, applies an adjustment voltage based on detection results, and outputs a corrected clock signal with accurate duty ratio. The intermediary duty adjustment circuit bridges the gap between the simple bias circuit and the requirement for high accuracy duty ratio adjustment under nonlinear distortion conditions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If a fixed bias voltage is used for duty ratio adjustment, then the circuit structure is simple, but duty ratio fluctuations occur due to process fluctuations in transistor thresholds

Engineering Contradiction:
Improvecircuit structure complexityVSAvoidduty ratio stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent transforms the static bias voltage into a dynamic adjustment mechanism. The duty adjustment circuit dynamically adjusts the adjustment voltage based on the detected duty ratio and process fluctuations in transistor thresholds. This dynamic adjustment compensates for manufacturing variations and ensures stable duty ratio performance across different process conditions, while maintaining relatively simple circuit structure through the use of existing oscillation and output circuits.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12034405B2Circuit device and oscillator
Publication Date: 2024.07.09 SEIKO EPSON CORP
  • US12034405B2 patent drawing
  • US12034405B2 patent drawing
  • US12034405B2 patent drawing

AI summary

A circuit device includes an oscillation circuit which is electrically coupled to a first node to electrically be coupled to one end of a resonator and a second node to electrically be coupled to another end of the resonator, and is configured to oscillate the resonator to generate an oscillation signal, and a waveform shaping circuit which is coupled to the first node, to which the oscillation signal is input from the first node, and which is configured to output a clock signal obtained by performing waveform shaping on the oscillation signal, and a duty adjustment circuit configured to supply the first node with a bias voltage which is variably adjusted based on adjustment data to thereby adjust a duty ratio of the clock signal.