Oscillator Clock Buffer Split for Duty Ratio Accuracy and Low EMI
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Solution Overview
Problem
Existing oscillation circuits face challenges in accurately calculating the duty ratio of clock signals outputted via external coupling terminals due to long rise and fall periods, leading to waveform distortion and complex correlation with DC voltage, making it difficult to maintain a 50% duty ratio.
Innovation Solution
The circuit apparatus includes an oscillation circuit with a first and second buffer circuit, where the rise period of the first clock signal is shorter than the second, allowing for accurate duty ratio calculation through a more linear correlation between duty ratio and DC bias, achieved by configuring the buffer circuits and RC filter to output clock signals with steep edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the clock signal is outputted via an external coupling terminal with a large load, then the EMI noise is reduced and the signal can be transmitted externally, but the rise and fall periods become long causing waveform distortion and making duty ratio calculation inaccurate
Solution Approach 1:
The patent divides the clock signal output into two separate paths: one path (first buffer circuit) provides a clock signal with short rise and fall periods for accurate duty ratio calculation and internal use, while the other path (second buffer circuit) provides a clock signal with long rise and fall periods for external output to reduce EMI noise. This segmentation allows each path to be optimized for its specific function without compromise.
2Object-affected harmful factors
If the clock signal has long rise and fall periods to reduce EMI noise, then the EMI noise is reduced, but the waveform becomes distorted from rectangular and the correlation between DC voltage and duty ratio becomes complicated
Solution Approach 1:
The patent separates the functions of EMI reduction and duty ratio indication into two different buffer circuits. The first buffer circuit maintains a rectangular waveform with sharp edges to preserve the linear correlation between DC voltage and duty ratio, while the second buffer circuit introduces gradual rise and fall periods for EMI reduction. This segmentation ensures that the complexity of waveform distortion does not affect duty ratio measurement accuracy.
3Device complexity
If a single buffer circuit is used to output the clock signal externally, then the device complexity is reduced, but the duty ratio cannot be accurately calculated when large load is coupled
Solution Approach 1:
The patent employs two parallel buffer circuits instead of a single buffer circuit. The first buffer circuit is dedicated to providing an internal clock signal with sharp edges for accurate duty ratio calculation, while the second buffer circuit handles external output with load-dependent waveform characteristics. This segmentation allows the system to maintain measurement precision without requiring complex compensation circuits.
Solution Approach 2:
The first buffer circuit acts as an intermediary between the oscillation circuit and the measurement system, providing a standardized clock signal with known characteristics for accurate duty ratio calculation. This intermediary buffer isolates the measurement function from the effects of external loading on the second buffer circuit.
Data Source
AI summary
A circuit apparatus includes an oscillation circuit that generates an oscillation signal, a first buffer circuit that outputs a first clock signal based on the oscillation signal, a second buffer circuit that outputs a second clock signal based on the first clock signal, a first terminal electrically couplable to a first node via which the first buffer circuit outputs the first clock signal, and a second terminal electrically coupled to a second node via which the second buffer circuit outputs the second clock signal, and the rise period of the first clock signal is shorter than the rise period of the second clock signal.