Relaxation Oscillator Circuit for Parasitic Capacitance Discharge
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Solution Overview
Problem
The maximum sampling frequency of relaxation oscillators is limited by the parasitic capacitance of the measured resistance, and existing solutions fail to completely remove this limitation.
Innovation Solution
A parasitic capacitance mitigation circuit is designed with a first switch coupled across the parasitic capacitance and a second switch between the capacitance and a reference voltage node. A pulse generator monitors the voltage across the capacitance, detects transients, and generates a pulse control signal to open the first switch and close the second switch, discharging the capacitance through the second switch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If variable gain is added to the oscillator to increase sampling frequency, then sampling frequency is improved, but the effect of parasitic capacitance is increased by the same gain factor
Solution Approach 1:
The patent extracts the parasitic capacitance from the main oscillator circuit by providing a separate discharge path through switch S2 connected to a reference voltage node. This allows the parasitic capacitance to be discharged independently through a dedicated circuit path, separating its management from the main oscillation mechanism and preventing it from limiting the sampling frequency.
Solution Approach 2:
The pulse generator detects voltage transients across the parasitic capacitance and generates control signals to open switch S1 and close switch S2 before the parasitic capacitance can significantly affect the oscillation. This preliminary discharge action prevents the parasitic capacitance from accumulating charge that would otherwise limit the sampling frequency.
2Speed
If a gain stage with gain G is added, then sampling frequency increases by G times, but parasitic capacitance effect increases by G times as well
Solution Approach 1:
The patent introduces switch S2 and the reference voltage node as intermediary elements that provide a dedicated discharge path for the parasitic capacitance. This intermediary circuit acts as a mediator between the parasitic capacitance and the rest of the oscillator, allowing the capacitance to be discharged through a separate channel that does not interfere with the main oscillation path, thereby enabling frequency multiplication without proportionally increasing the parasitic effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The mitigation circuit increases the oscillation frequency of the relaxation oscillator by discharging the parasitic capacitance, effectively improving the sampling frequency while minimizing the impact of parasitic capacitance.
Implementation Method 1
the second switch closes to discharge the parasitic capacitance through the second switch
Data Source
AI summary
A parasitic capacitance mitigation circuit for a relaxation oscillator. The parasitic capacitance mitigation circuit includes a first switch coupled across a parasitic capacitance of a resistive sensing element and a second switch coupled between the parasitic capacitance and a reference voltage node. The parasitic capacitance mitigation circuit includes a pulse generator configured to: monitor a voltage across the parasitic capacitance; detect a voltage transient across the parasitic capacitance; and generate a pulse control signal in response to detecting the voltage transient. In response to the pulse control signal, the first switch opens and the second switch closes to discharge the parasitic capacitance through the second switch.