Oscillator Crystal Cut-Off Structure for Frequency Offset Reduction
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Solution Overview
Problem
Existing packaging technologies for quartz crystal oscillators face challenges in miniaturization, thermal stress, and electrical connection limitations, leading to reduced testing yields and increased thermal expansion coefficient mismatches, which affect frequency stability and impedance.
Innovation Solution
A novel oscillator crystal structure with internal cut-off regions formed by etching processes, encapsulated within a wafer-level-package structure using a capping and bottom layer with similar thermal expansion coefficients, and integrated metal vias for electrical connections, reducing thermal stress and improving impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cavity packaging is used to accommodate the quartz crystal, then the packaging structure can support the crystal, but the cavity spacing constraints cut off the area for providing sufficient electrical connections and make the test process much more difficult, causing decrease in testing yields
Solution Approach 1:
The patent divides the packaging structure into multiple functional regions: a first region with a cavity for accommodating the quartz crystal, and a second region without a cavity for providing electrical connections and testing. This segmentation allows each region to serve its specific function optimally without interference, resolving the contradiction between structural support and electrical connection accessibility.
2Volume of moving object
If wafer-level packaging is used to reduce packaging size, then smaller packaging size and better electrical performances are achieved, but thermal expansion coefficients mismatch between different materials and heat dissipation issues occur
Solution Approach 1:
The patent applies different material properties to different regions of the packaging structure. The first region containing the quartz crystal uses materials with matched thermal expansion coefficients to minimize thermal stress, while the second region uses materials optimized for heat dissipation and electrical performance. This local differentiation resolves the contradiction between miniaturization and thermal management.
3Ease of operation
If three-dimensional packaging with TSV process is used to shorten electrical transmitting length, then electrical connections are improved, but thermal expansion coefficients mismatch and thermal stress concentration occur in the wafer packaging structure
Solution Approach 1:
The patent transitions from traditional planar electrical connections to three-dimensional vertical connections using through-silicon vias (TSVs). This dimensional change allows electrical signals to traverse shorter paths through the wafer thickness, improving connection efficiency while the segmented structure with matched thermal expansion materials mitigates the resulting thermal stress concentration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances frequency stability, reduces thermal stress, and improves electrical connections, resulting in better impedance and component characteristics, while minimizing frequency offset and thermal expansion issues.
Implementation Method 1
the internal cut-off region is implemented by adopting an etching process
Implementation Method 2
taking a quartz crystal piezoelectric element as an oscillator provides an outstanding accuracy and stability
Data Source
AI summary
An oscillator wafer-level-package structure and oscillator crystal structure having internal cut-off region thereof are provided. At least one cut-off region is formed inside the oscillator crystal structure, penetrating its upper and lower surface, such that the crystal main region and its adjacent region are separated. A bottom layer includes an upper plane. A capping layer includes a lower plane, and the oscillator crystal structure is disposed there in between, forming an upper and lower cavity with the capping layer and the bottom layer. By engaging an upper and lower seal ring surrounding the oscillator crystal structure, the oscillator crystal structure is sealed, forming the wafer-level-package structure. By designing internal cut-off region inside the oscillator crystal structure, frequency offset after encapsulation is reduced, and better device characteristics are obtained.