Oscillator Failure Monitor Using Capacitor Discharge Alarm
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Solution Overview
Problem
Digital devices with external frequency determining elements/oscillators face power consumption issues due to the need for watchdog timers as failsafes, which either keep processors awake or increase sleep current consumption, as they cannot reliably monitor the external oscillator's operation without excessive power usage.
Innovation Solution
A delay and monitoring circuit that charges to a first logic level when the external frequency determining element/oscillator is operational and discharges to a second logic level if it fails, using a voltage storage capacitor and comparator to alert the processor and switch to a backup clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a watchdog timer is enabled to monitor the external oscillator, then the reliability of the digital device is improved, but the sleep current consumption increases excessively
Solution Approach 1:
The monitoring function is extracted from the processor and implemented as a separate, dedicated monitoring circuit that operates independently during sleep mode. This circuit uses minimal power while providing continuous oscillator monitoring, resolving the contradiction between reliability and power consumption.
Solution Approach 2:
A dedicated monitoring circuit acts as an intermediary between the external oscillator and the processor. This intermediary circuit continuously monitors the oscillator during sleep mode and only wakes the processor when actual failure is detected, eliminating the need for high-power watchdog timers while maintaining reliability.
2Reliability
If the processor remains awake to verify external oscillator operation, then the reliability is improved, but the power consumption increases
Solution Approach 1:
The monitoring circuit performs preliminary continuous verification of oscillator operation during sleep mode before the processor needs to wake up. This preliminary action ensures the oscillator is functioning without requiring the processor to remain awake, thus maintaining reliability while minimizing power consumption.
Solution Approach 2:
The monitoring circuit performs periodic verification of the oscillator at low power intervals during sleep mode, only triggering a processor wake-up when verification fails. This periodic monitoring approach maintains reliability while allowing the processor to remain in low-power state during normal operation.
3Reliability
If the processor wakes up frequently to check oscillator status, then the reliability is improved, but the productivity decreases due to increased wake-up interruptions
Solution Approach 1:
A dedicated monitoring circuit serves as an intermediary that continuously monitors the oscillator without requiring frequent processor wake-ups. This intermediary handles routine monitoring tasks, allowing the processor to maintain deep sleep states and improving productivity while preserving monitoring reliability.
Solution Approach 2:
The monitoring circuit is self-sufficient, operating independently during sleep mode to monitor the oscillator without requiring processor intervention. It only involves the processor when actual failures occur, thus maintaining high reliability while maximizing processor productivity during sleep periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows the processor to wake up from sleep mode and alert the system to switch to a backup clock when the external oscillator fails, reducing power consumption and ensuring reliable operation without the need for excessive watchdog timer usage.
Implementation Method 1
a voltage storage capacitor connected to the diode, wherein the voltage storage capacitor is charged to a voltage through the diode and from the plurality of clock pulses
Implementation Method 2
a current sink connected to the voltage storage capacitor, wherein the current sink discharges the voltage on the voltage storage capacitor when not being charged from the plurality of clock pulses
Implementation Method 3
a voltage comparator having an output connected to an input of the processor, a first input connected to the voltage storage capacitor and a second input connected to a reference voltage, wherein when the voltage on the voltage storage capacitor is greater than the reference voltage the output of the voltage comparator is at a first logic level
Data Source
AI summary
A failsafe oscillator monitor and alarm circuit receives clock pulses from an external oscillator that if a failure thereto occurs, the failsafe oscillator monitor and alarm circuit will notify a digital processor of the external oscillator failure. The failsafe oscillator monitor and alarm circuit is a very low current usage circuit that charges a storage capacitor with clock pulses from the external oscillator when functioning normally and discharges the storage capacitor with a constant current sink if the external oscillator stops functioning. When the voltage charge on the storage capacitor becomes less than a reference voltage an alarm signal is sent to the digital processor for exception or error handling of the failed external oscillator.