Oscillator Logic Separation for Short-Circuit Clock Reliability

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Solution Overview

Problem

Existing oscillators face reliability issues due to short circuit failures between the output control terminal and the failure diagnosis terminal, which can cause clock output to stop, especially in miniaturized electronic devices where adhesion of dust or electrochemical migration increases the risk of such failures.

Innovation Solution

The oscillator design includes a failure diagnosis terminal that outputs a signal with a different logic than the output control terminal, allowing for continued clock signal output even if a short circuit occurs, by configuring the output control terminal to receive a positive or negative logic signal and the failure diagnosis terminal to output the other logic, thereby preventing clock signal stoppage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the output control terminal and failure diagnosis terminal use the same logic level, then the circuit design is simplified, but a short circuit between these terminals causes clock output to stop

Engineering Contradiction:
Improvecircuit design complexityVSAvoidclock output reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies asymmetry by making the logic levels of the output control terminal and failure diagnosis terminal different from each other. Specifically, when the output control terminal receives a positive logic signal, the failure diagnosis terminal outputs a negative logic signal, and vice versa. This asymmetric logic level design prevents short circuit failures from causing clock output stoppage while maintaining relatively simple circuit design.

Inventive Principle:
Principle #4Asymmetry

2Volume of moving object

If electronic devices are miniaturized with high-density component arrangement, then device size is reduced, but the risk of short circuit failures due to dust adhesion or electrochemical migration increases

Engineering Contradiction:
Improvedevice sizeVSAvoidshort circuit resistance
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent applies preliminary anti-action by designing the output control terminal and failure diagnosis terminal with different logic levels in advance. This preliminary design prevents the harmful effect of short circuit failures before they can occur. When a short circuit does happen due to dust adhesion or electrochemical migration in miniaturized devices, the different logic levels ensure that the clock output is not stopped, thus preventing the adverse effect beforehand.

Inventive Principle:
Principle #9Preliminary anti-action

3Reliability

If the oscillator provides failure diagnosis capability, then reliability monitoring is improved, but the terminal arrangement and signal output mode become more complex

Engineering Contradiction:
Improvefailure detection capabilityVSAvoidterminal arrangement complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by making the failure diagnosis terminal multi-functional. The terminal not only provides failure diagnosis capability but also can be used for clock output control. By configuring the failure diagnosis terminal to output signals with different logic levels based on the output control terminal's input, the patent achieves reliable failure detection while avoiding excessive terminal arrangement complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240210469A1Oscillator And Electronic Device
Publication Date: 2024.06.27 SEIKO EPSON CORP
  • US20240210469A1 patent drawing
  • US20240210469A1 patent drawing
  • US20240210469A1 patent drawing

AI summary

An oscillator includes a power supply terminal to which a high-potential-side power supply voltage is supplied, a ground terminal to which a low-potential-side power supply voltage is supplied, a clock terminal that outputs a clock signal, an output control terminal to which an output control signal of the clock signal is input, and a failure diagnosis terminal that outputs a failure diagnosis signal. The output control terminal receives the output control signal having a first logic which is one of a positive logic and a negative logic, and the failure diagnosis terminal outputs the failure diagnosis signal having a second logic which is the other one of the positive logic and the negative logic.