Oscillator Clock Shutdown Sequencing for Low-Power Wake-Up
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Solution Overview
Problem
Conventional embedded oscillator systems consume significant power in low power mode due to the use of a low frequency clock source, necessitating a solution to reduce power consumption while maintaining correct operation upon wake-up.
Innovation Solution
An oscillator control system with a controller that transitions from a first mode to a second low power mode by disabling the oscillator and system clock signals after specific time periods, allowing system processes to close before disabling the oscillator, and uses counters to manage these transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a low frequency clock source is used to enable wake-up from low power mode, then the system can maintain synchronous operation, but power consumption increases significantly
Solution Approach 1:
The system performs preliminary actions by disabling the oscillator and system clock before actually entering low power mode, and by using wake-up triggers that are prepared in advance. This allows the system to fully shut down clock sources while maintaining the ability to wake up synchronously when needed.
Solution Approach 2:
The system dynamically adjusts its operational state by transitioning between different power modes based on activity requirements. The oscillator controller dynamically enables or disables the oscillator and system clock based on whether the system needs to be in high power mode for synchronous operations or can enter low power mode, making the clock system adaptive rather than static.
2Use of energy by moving object
If the oscillator is disabled immediately to save power, then power consumption is reduced, but system processes may not have time to close properly
Solution Approach 1:
The system gives advance notice to processes that the oscillator will be disabled by disabling the system clock first, allowing processes to complete their operations and close properly before the oscillator shuts down. This preliminary clock disablement serves as a warning signal for process termination.
Solution Approach 2:
The system clock acts as an intermediary between the oscillator and the processes running on the system. By disabling the system clock first, it mediates the transition by signaling processes to close before the oscillator is disabled, ensuring proper process completion while still achieving power savings.
3Ease of operation
If the system maintains a low frequency clock source in low power mode, then wake-up to high power mode is enabled, but the oscillator cannot be fully disabled
Solution Approach 1:
The system extracts and removes the low frequency clock source requirement by implementing wake-up triggers that do not depend on a continuously running clock. This allows the oscillator to be fully disabled in low power mode while maintaining wake-up capability through alternative mechanisms such as external triggers or internal wake-up sources.
Solution Approach 2:
The system uses disposable or temporary wake-up triggers that do not require a persistent clock source. These triggers can be set up before entering low power mode and can activate the system without requiring a continuously running low frequency clock, allowing the oscillator to be fully shut down.
Data Source
AI summary
The disclosure relates to an oscillator control system with dynamic control for power saving. Example embodiments include an oscillator control system comprising: an oscillator configured to provide an oscillator clock signal (osc_clk) in response to receiving an oscillator enable signal (en_osc); a system clock signal generator configured to generate a system clock signal (sys_clk); a system controller connected to receive a system clock signal (sys_clk) from the clock signal generator; and an oscillator controller configured to provide the oscillator enable signal (en_osc) to the oscillator and receive the oscillator clock signal (osc_clk), to receive the system clock signal (sys_clk) from the clock signal generator and a system mode signal (sys_mode) from the system controller, and to receive a first change of state signal from an input of the oscillator control system, wherein the oscillator controller, on receiving the first change of state signal, is configured to transition the oscillator control system from a first mode in which the oscillator clock signal and system clock signal are enabled to a second mode in which the oscillator clock signal and system clock signal are disabled by disabling the system clock signal (clk_enable) after a first set time period from receiving the change of state signal and to disable the oscillator enable signal (en_osc) after a second set time period following the first set time period.