Oscillator Clock Output Control for Stable Startup Duty
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Solution Overview
Problem
Existing oscillators face challenges in maintaining stable clock signal duty during startup, particularly under environmental and process variations, which can lead to inadequate performance in temperature-compensated crystal oscillators (TCXOs) and oven-controlled crystal oscillators (OCXOs).
Innovation Solution
A circuit device comprising a first oscillation circuit, a second oscillation circuit, a clock signal output circuit, and an output control circuit, where the output control circuit includes a counter circuit that generates an output enable signal based on the output signal of the second oscillation circuit, ensuring the clock signal is output only when the oscillation state is stable, thereby maintaining appropriate duty and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an analog integration process is used to control clock signal output during startup, then the circuit can be simple, but it cannot handle broad environmental and process variations to ensure appropriate duty
Solution Approach 1:
The patent replaces the analog integration process with a digital counting process. The counter circuit counts oscillation signals to determine startup completion, substituting continuous analog voltage integration with discrete digital counting. This enables precise control of clock signal duty during startup while maintaining circuit simplicity, as the digital approach naturally handles environmental and process variations without requiring complex analog compensation.
2Speed
If the clock signal is output immediately after oscillation starts, then the response time is fast, but the duty may be inappropriate due to insufficient oscillation signal growth
Solution Approach 1:
The patent implements preliminary counting of oscillation signals before enabling clock signal output. The counter circuit accumulates a predetermined number of oscillation signals, ensuring the oscillation has grown sufficiently before the clock signal is output. This preliminary action guarantees appropriate duty precision while maintaining fast startup response, as the counting process completes quickly once oscillation begins.
3Speed
If a counter is used to accelerate startup by increasing bias current, then startup speed improves, but the counter controls bias current rather than clock signal output timing
Solution Approach 1:
The patent makes the counter circuit universal by using it for clock signal output timing control rather than solely for bias current acceleration. The same counter that could track startup progression is used to generate the output enable signal, eliminating the need for separate control mechanisms. This multi-functional use maintains startup acceleration capability while adding precise clock signal timing control, enhancing overall system adaptability.
Data Source
AI summary
A circuit device includes a first oscillation circuit, a second oscillation circuit, a clock signal output circuit adapted to output a clock signal based on an output signal of the first oscillation circuit, and an output control circuit adapted to perform output control of the clock signal output circuit. The output control circuit includes a counter circuit adapted to perform a counting process based on an output signal of the second oscillation circuit, and the counter circuit outputs an output enable signal of the clock signal to the clock signal output circuit based on a result of the counting process.