OTA Offset Cancellation Through Reconfigurable Transistor Matching
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Solution Overview
Problem
Operational amplifiers (opamps) suffer from input referred offset due to manufacturing process variations, which introduces errors in circuits using them, necessitating a method to reduce this offset.
Innovation Solution
The implementation of configuration units with switches in operational transconductance amplifiers (OTAs) allows for post-manufacture calibration of transistors to achieve balance between groups A and B, reducing offset, and the application of a gain modifier to further minimize offset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If transistors are manufactured using standard processes, then manufacturing cost and simplicity are maintained, but input referred offset increases due to process variations
Solution Approach 1:
The transistor is divided into multiple parallel channels (first channel, second channel, third channel, fourth channel) with configurable connectivity. Configuration circuits can selectively connect these channels to form different transistor groups, allowing post-manufacture optimization of transistor matching without requiring precision manufacturing of individual transistors.
Solution Approach 2:
The circuit employs dynamic reconfigurability through configuration circuits that can change the connectivity of transistor channels based on measured performance. This allows the transistor configuration to be optimized after manufacture by selecting which channels to connect in parallel to achieve desired matching characteristics.
2Reliability
If transistor configurations are fixed during manufacture, then device complexity is reduced, but offset cancellation capability is lost
Solution Approach 1:
The configuration circuits and switching mechanisms are pre-integrated into the transistor structure during manufacture, but remain inactive or in a default state. The actual configuration optimization is performed later based on measured offset characteristics, allowing the hardware to be prepared in advance without adding immediate complexity.
Solution Approach 2:
The system performs self-calibration by measuring its own offset characteristics and automatically adjusting the transistor configuration to minimize offset. The configuration circuits use the measured offset information to determine the optimal connectivity configuration without requiring external intervention.
3Strength
If all transistor channels are connected in parallel, then transistor strength is increased, but offset may worsen due to imbalance
Solution Approach 1:
Different channels are treated differently based on their individual characteristics. The configuration circuits selectively connect specific channels in parallel based on measured performance, allowing each channel to contribute optimally to the overall transistor strength while maintaining balance. Not all channels are connected to all transistors - connections are made locally based on performance requirements.
Solution Approach 2:
The system changes the effective parameters of the transistor by selectively enabling or disabling connections between channels and transistors. This allows optimization of both strength and balance by adjusting which channels are active and how they are connected, rather than using a fixed configuration for all devices.
Data Source
AI summary
A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset.