OTP Anti-Fuse Cell With Integrated Precharge Transistor
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Solution Overview
Problem
Existing anti-fuse memory cells require high voltages for programming, leading to large chip area occupation by level shifters and high voltage transistors, which is inefficient in terms of power consumption and integration in mobile devices, especially in IoT applications where low power and small size are crucial.
Innovation Solution
A low voltage anti-fuse memory cell with an integrated active precharge device that reduces write disturb to non-selected memory cells by using a longer channel precharge transistor to raise the voltage of the channel region during programming, allowing for programming at lower voltages and minimizing the area occupied by high voltage peripherals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage programming is used in anti-fuse memory cells, then reliable data storage is achieved, but large chip area is occupied by level shifters and high voltage transistors
Solution Approach 1:
The patent merges the precharge transistor and anti-fuse device into a single integrated structure, where the precharge transistor's channel region directly forms the anti-fuse device. This integration eliminates the need for separate high voltage transistors and level shifters, reducing chip area while maintaining programming reliability through the inherent high voltage capability of the merged structure.
Solution Approach 2:
The integrated precharge transistor-anti-fuse device structure serves multiple functions: it acts as both the precharge transistor for write disturb protection and the anti-fuse device for data storage. This multi-functionality eliminates the need for separate dedicated high voltage programming circuits, thereby reducing overall chip area occupation.
2Ease of operation
If high voltage transistors and level shifters are added to anti-fuse memory cells, then programming capability is improved, but power consumption increases
Solution Approach 1:
By merging the precharge transistor and anti-fuse device, the patent eliminates separate high voltage programming circuits that would consume additional power. The integrated structure achieves programming capability through the inherent high voltage tolerance of the merged device, reducing overall power consumption.
3Ease of manufacture
If standard CMOS process is used for anti-fuse memory, then manufacturing simplicity is maintained, but write disturb to non-selected cells occurs
Solution Approach 1:
The patent applies local quality by creating a longer channel region in the precharge transistor that is specifically optimized for write disturb protection. This longer channel raises the voltage of the channel region during programming, preventing unintended programming of non-selected cells, while the rest of the device maintains standard CMOS characteristics for ease of manufacture.
Solution Approach 2:
The precharge transistor performs preliminary action by raising the channel region voltage before the actual programming operation. This preliminary voltage raise prevents write disturb to non-selected cells during the subsequent programming process, while maintaining compatibility with standard CMOS manufacturing.
Data Source
AI summary
A one-time programmable (OTP) memory device includes a memory array having multiple memory elements. The memory array includes a plurality of anti-fuse FinFETs and a plurality of access FinFETs. Each anti-fuse device has a first terminal for receiving a programming voltage and a second terminal. The anti-fuse FinFETs are located in a first region of an integrated circuit. At least one anti-fuse FinFET of the plurality of anti-fuse FinFETs and at least one access FinFET of the plurality of access FinFETs form a memory element of the plurality of memory elements of the memory array. Each access FinFET is configured to selectively couple one of a program inhibit voltage and a program enable voltage to the second terminal of a corresponding anti-fuse FinFET in a programming operation. The access FinFETs are located in a second region of the integrated circuit, different than the first region of the integrated circuit.