OTP Anti-Fuse Memory Cell Layout for Low-Voltage PUF Generation

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Solution Overview

Problem

Existing integrated circuits (ICs) with one-time-programmable (OTP) memories face challenges in generating unique PUF signatures due to manufacturing variability, which are not effectively leveraged for authentication and secret key storage, and require high programming voltages, leading to high power consumption and reduced device lifetime.

Innovation Solution

Implementing anti-fuse memory cells with symmetrical configurations and symmetrical transistors, where the gate dielectric layer has two portions that randomly break down, allowing for the generation of unique PUF signatures at lower programming voltages, reducing power consumption and enhancing device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If anti-fuse memory cells use conventional asymmetrical configurations, then programming can be achieved, but manufacturing variability cannot be effectively leveraged for unique PUF signatures and power consumption remains high

Engineering Contradiction:

ImprovePUF signature uniquenessVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies asymmetry in reverse - it uses symmetrical transistor configurations (both transistors having identical dimensions, materials, and structures) to exploit manufacturing variability. The symmetry ensures that random variations during fabrication create unique, unpredictable breakdown patterns in the gate dielectric, generating distinctive PUF signatures while maintaining low programming voltages and power consumption.

Inventive Principle:

Principle #4Asymmetry

Solution Approach 2:

The patent changes the critical parameter from asymmetrical transistor dimensions to symmetrical dimensions with controlled gate dielectric properties. By adjusting the gate dielectric layer thickness and material composition, the system enables breakdown at lower programming voltages while the symmetrical configuration ensures that manufacturing variability produces unique PUF signatures for authentication.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If high programming voltages are applied to OTP memories, then reliable programming can be achieved, but power consumption increases and device lifetime is reduced

Engineering Contradiction:

Improveprogramming reliabilityVSAvoiddevice lifetime

Core Design Contradiction:

ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent fundamentally changes the voltage parameter by using symmetrical transistor configurations that enable breakdown at lower voltages. The symmetrical structure ensures uniform electric field distribution, allowing reliable programming at reduced voltage levels, which decreases power consumption and reduces stress on the device, thereby extending operational lifetime.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If manufacturing variability is not leveraged, then mass production is simplified, but unique PUF signatures for authentication cannot be generated

Engineering Contradiction:

Improveauthentication securityVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent uses symmetrical configurations to convert manufacturing variability from a challenge into an opportunity. The identical transistor structures ensure that random variations in fabrication create unique, reproducible PUF signatures. This approach maintains standard manufacturing processes while enabling secure authentication through the inherent uniqueness of each device's physical characteristics.

Inventive Principle:

Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables the generation of unique PUF signatures with reduced power consumption and improved device lifetime by leveraging manufacturing variability, while maintaining efficient programming and reading performance.

Implementation Method 1

a gate dielectric layer under the gate terminal and including a first portion and a second portion. During a programming process, a programming voltage is applied on the gate terminal to break down either the first portion or the second portion of the gate dielectric layer

Methodology Applied

Scientific EffectDielectric breakdown: Avalanche Breakdown

Data Source

PatentUS12588512B2Generation of physically unclonable function using one-time-programmable memory devices with backside interconnect structures

Publication Date: 2026.03.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a memory cell randomly presenting a first logic state or a second logic state and formed on a first side of a substrate, and a first and a second bit lines formed on a second side of the substrate opposite to the first side. The memory cell includes: a programming transistor having a first and a second source/drain terminals; a first reading transistor having a first source/drain terminal coupled to the first source/drain terminal of the programming transistor; and a second reading transistor having a first source/drain terminal coupled to the second source/drain terminal of the programming transistor. The first bit line is operatively coupled to a second source/drain terminal of the first reading transistor, and the second bit line is operatively coupled to a second source/drain terminal of the second reading transistor.