Anti-Fuse OTP Memory Cell Layout for Single Breakdown Mode
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Solution Overview
Problem
The high complexity and cost associated with manufacturing non-volatile memory devices, particularly one-time programmable (OTP) devices, due to their distinct manufacturing techniques which differ from standard logic processes, limit their efficiency and reliability.
Innovation Solution
The development of a memory device with an anti-fuse element connected to a transistor, where the gate via is positioned close to the channel of the anti-fuse element, allowing for a single programming mode and improved manufacturing processes such as photolithography and self-aligned processes to pattern fins, enabling efficient formation of finFET transistors on a bulk silicon substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional non-volatile memory manufacturing techniques are used, then one-time programmable memory functionality is achieved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent merges the formation of anti-fuse elements and transistors into a unified manufacturing process using standard CMOS techniques. Both structures are formed simultaneously through shared process steps including fin formation, dielectric layer deposition, and patterning, eliminating the need for separate specialized processing lines and reducing overall manufacturing complexity.
Solution Approach 2:
The invention uses universal standard logic process techniques to form both anti-fuse elements and transistors. The same photolithography, etching, and deposition processes used for transistor fabrication are also applied to create anti-fuse structures, allowing standard logic fabrication facilities to produce OTP memory without requiring dedicated specialized equipment or processes.
2Reliability
If specialized non-volatile memory manufacturing processes are used, then anti-fuse element formation is achieved, but production cost increases
Solution Approach 1:
The patent modifies standard CMOS process parameters to enable anti-fuse element formation. Specifically, it adjusts dielectric layer thickness, patterning dimensions, and etch conditions within the existing process window to create the anti-fuse structure, rather than introducing entirely new process steps or requiring specialized equipment that would increase production costs.
Solution Approach 2:
The manufacturing process uses self-aligned techniques where previously formed structures serve as alignment references for subsequent steps. The fin structures and dielectric layers formed for transistor creation automatically provide alignment guidance for anti-fuse element formation, eliminating the need for additional alignment equipment or complex registration processes.
3Adaptability or versatility
If gate via is positioned far from anti-fuse channel, then multiple programming modes are possible, but device area increases
Solution Approach 1:
The patent employs an asymmetric via configuration where the gate via is deliberately positioned offset from the center of the anti-fuse element, specifically closer to one end of the channel. This asymmetric placement creates a unique electrical field distribution that enables controlled breakdown and programming while minimizing the lateral space required for via formation and connection.
Solution Approach 2:
The gate via serves as an intermediary element that provides both structural support and electrical connection functionality. By positioning the via to overlap partially with the anti-fuse channel region, it acts as a mediator that delivers programming voltage directly to the channel while maintaining compact geometry, thus achieving programming capability without requiring separate dedicated contact structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a memory device with a single breakdown mode, enhancing cell characterization and reliability, while maintaining a straightforward manufacturing process, thus addressing the complexity and cost issues of traditional non-volatile memory production.
Implementation Method 1
This configuration results in a memory device with a single breakdown mode, enhancing cell characterization and reliability
Data Source
AI summary
A memory device includes a transistor, an anti-fuse element, a source/drain contact, a first gate via, and a second gate via. The transistor is over a substrate. The anti-fuse element is over the substrate and is connected to the transistor in series. The source/drain contact is connected to a source/drain region of the transistor. The first gate via is connected to a first gate structure of the transistor. The first gate structure of the transistor extends along a first direction in a top view. The second gate via is connected to a second gate structure of the anti-fuse element. The second gate via is between the first gate via and the source/drain contact along the first direction in the top view.