OTP Cell Array Converging Circuit for Sense Amplifier Area Reduction
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Solution Overview
Problem
Existing semiconductor memory devices with One Time Programmable (OTP) cell arrays face challenges in efficiently amplifying signals due to the large area occupied by sense amplifier circuits, especially as the number of bit lines increases, leading to signal detection difficulties and increased resistance values, which complicates data storage and retrieval.
Innovation Solution
The implementation of a semiconductor memory device with an improved arrangement structure that includes a converging circuit and a sense amplifier circuit, where the converging circuit connects multiple bit lines to reduce the number of sense amplifiers needed, thereby minimizing the area occupied by the sense amplifier circuit and enhancing signal amplification efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bit lines is increased to expand storage capacity, then the data storage capability is improved, but the area occupied by sense amplifier circuits increases and signal detection becomes more difficult
Solution Approach 1:
Multiple bit lines are merged and connected to a common node, allowing multiple OTP cells to share a single sense amplifier. This consolidation reduces the total number of sense amplifiers required, thereby decreasing the overall circuit area while maintaining expanded storage capacity through the increased number of bit lines.
2Quantity of substance
If the number of bit lines is increased to expand storage capacity, then the data storage capability is improved, but signal detection difficulty increases due to increased resistance values
Solution Approach 1:
By merging multiple bit lines at a common node, the sense amplifier detects the collective signal from multiple OTP cells rather than individual cell signals. This aggregation of signals improves the signal-to-noise ratio and makes detection easier despite the increased resistance values associated with more bit lines.
3Measurement precision
If multiple sense amplifiers are used to handle increased bit lines, then signal detection capability is improved, but the area occupied by sense amplifier circuit increases
Solution Approach 1:
Instead of using multiple sense amplifiers for multiple bit lines, the patent merges multiple bit lines to a common node and uses a single sense amplifier. This approach maintains signal detection capability by aggregating signals at the common node while significantly reducing the circuit area by eliminating the need for multiple sense amplifiers.
4Quantity of substance
If bit lines are extended to connect more OTP cells, then storage capacity is improved, but resistance values increase complicating data retrieval
Solution Approach 1:
Multiple bit lines are merged at a common node, which aggregates the signals from extended bit lines connecting to more OTP cells. This merging reduces the effective resistance impact on data retrieval by providing multiple parallel signal paths that converge at the common node, improving reliability despite extended bit line connections.
Data Source
AI summary
Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.