OTP Memory Fuse Layout Across Metallization Layers for Key Security
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Solution Overview
Problem
Existing one-time-programmable (OTP) memory devices face security vulnerabilities due to the ease of decrypting keys stored across efuse memory cells by identifying blown and intact fuse resistors through reverse-engineering, as these resistors are typically formed in common metallization layers.
Innovation Solution
The OTP memory device incorporates fuse resistors across different metallization layers, both frontside and backside, with each efuse memory cell having multiple resistors spread vertically, making it difficult to identify which resistors belong to a specific cell, thereby enhancing security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fuse resistors are formed in common metallization layers, then manufacturing process is simple, but security is compromised due to ease of reverse-engineering
Solution Approach 1:
The patent transitions fuse resistors from a two-dimensional planar arrangement in common metallization layers to a three-dimensional vertical distribution across multiple stacked metallization layers. This dimensional change makes reverse-engineering significantly more difficult as attackers must now analyze and correlate resistors across multiple layers, while the manufacturing process remains compatible with existing semiconductor fabrication techniques through standard layer-by-layer processing
Solution Approach 2:
The patent segments the fuse resistors that were previously grouped together in single metallization layers and distributes them across multiple stacked metallization layers. Each efuse memory cell's resistors are divided and placed in different vertical positions, making it difficult to identify which resistors belong to a specific cell through reverse-engineering, while maintaining manufacturing simplicity through standard semiconductor fabrication processes
2Reliability
If fuse resistors are distributed across multiple metallization layers, then security is enhanced, but device complexity increases
Solution Approach 1:
The patent merges the formation of fuse resistors with the existing multi-layer metallization structure used for word lines and bit lines. By integrating efuse resistors into the same stacked metallization layers that already exist for memory cell access, the patent enhances security through vertical distribution without adding separate dedicated structures, thereby limiting the increase in device complexity
Data Source
AI summary
A method for fabricating a memory device is disclosed herein. The method includes forming a transistor along a frontside surface of a substrate, forming a first fuse resistor in a first metallization layer that is vertically disposed with respect to the frontside surface, and forming a second fuse resistor in a second metallization layer that is vertically disposed with respect to the frontside surface. The first metallization layer being different from the second metallization layer. The second fuse resistor and the first fuse resistor are each coupled to the transistor.