OTP Memory Fuse Layout for Low-Current Electromigration Programming
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Solution Overview
Problem
Existing OTP memory devices face challenges in breaking metal wires due to the surrounding SiO2 material, which dissipates heat rapidly, making it difficult to reach the electromigration limit and requiring high current for programming.
Innovation Solution
The SiO2 material is removed around the metal wires, allowing the use of vapor HF (vHF) to expose the wires, enabling them to reach the electromigration limit with lower current, and simplifying the driving electronics by integrating with ASICs without dedicated areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiO2 material surrounds the metal wires, then the structure is stable and protected, but heat dissipates rapidly making it difficult to reach electromigration limit
Solution Approach 1:
The patent removes SiO2 material from specific regions surrounding the metal wires where current is applied. This extraction allows heat to be retained in the metal wire during programming operations, enabling the wire to reach electromigration limit and break reliably, while SiO2 remains in other areas to provide structural stability and protection.
Solution Approach 2:
The patent applies different SiO2 material distributions to different regions of the device. In programming regions, SiO2 is removed to enable heat retention and wire breaking. In non-programming regions, SiO2 remains to provide structural support and protection. This local differentiation resolves the contradiction between structural stability and heat retention.
2Reliability
If high current is used to blow the metal wire, then the wire breaks reliably, but the driving electronics become complex requiring dedicated current generation areas
Solution Approach 1:
The patent utilizes the harmful effect of heat (which was previously dissipated by surrounding SiO2) by removing SiO2 to enable heat retention. This converts the previously harmful heat dissipation into a beneficial effect that enables reliable wire breaking at lower currents, eliminating the need for complex high-current driving electronics.
Solution Approach 2:
The patent changes the physical parameters of the programming process by modifying the thermal environment around the metal wire. Removing SiO2 changes the heat dissipation parameter, allowing the same current to produce higher temperatures in the wire, thereby achieving reliable breaking at lower current levels and simplifying driving electronics.
3Strength
If wider metal wires are used, then the structure is more robust, but the area density decreases
Solution Approach 1:
The patent changes the thermal parameter of the wire environment by removing SiO2, which increases the temperature coefficient of the wire. This allows narrower wires to achieve the same breaking effect as wider wires would have in a SiO2-surrounded environment, thereby maintaining wire robustness while improving area density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the current required for programming, allows for narrower connecting wires, and achieves high area density without needing a dedicated element for current generation, simplifying the driving circuit and integrating with ASICs.
Implementation Method 1
The etching medium may include vapour HF (vHF). The second portion of the SiO2 material may be removed by the etching medium.
Implementation Method 2
The etching medium may include vapour HF (vHF).
Implementation Method 3
E-fuse uses a high current to blow a metal wire... I-fuse is similar to e-fuse, but it uses optimized electronics that require less current until the wire reaches its electromigration limit.
Implementation Method 4
I-fuse is similar to e-fuse, but it uses optimized electronics that require less current until the wire reaches its electromigration limit.
Data Source
AI summary
An example one-time programmable (OTP) memory device is provided. The OTP memory device include a passivation layer. A top metal layer is positioned below the passivation layer. The top metal layer includes one or more holes configured to an etching medium to pass through the holes. An array of memory elements is positioned in a memory layer below the top metal layer. A first metal address line layer is positioned below the array of memory elements and includes a plurality of first address lines extending in a first direction. A first end of each memory element being connected to one of the plurality of first metal address lines. A second metal address line layer is positioned below the first metal address line layer and includes a plurality of second metal address lines extending in a second direction. The second direction is different than the first direction.


