OTP Memory Gate Structure With Dual-Step STI Field Concentration
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Solution Overview
Problem
Current one-time programmable (OTP) memory devices have weak reading current and longer stress time under program mode, limiting their performance and fabrication cost-effectiveness.
Innovation Solution
A method for fabricating semiconductor devices involves forming shallow trench isolation (STI) with specific step profiles on the substrate, followed by sequential gate oxide layer formation and gate structure creation, which enhances the electrical field concentration and device architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional OTP memory device architecture is used, then fabrication cost is low and storage is easy, but reading current is weak and stress time is long
Solution Approach 1:
The patent applies local quality by creating different step profiles at different locations of the substrate. Specifically, corners of the substrate have both a first step (from STI removal) and a second step (from gate oxide removal), while other areas have only the first step. This localized structural differentiation concentrates the electrical field precisely where needed to enhance reading current and reduce stress time without affecting the entire device uniformly.
Solution Approach 2:
The patent introduces dimensional changes by creating multi-level step profiles on the substrate surface. The combination of first steps (from STI removal) and second steps (from gate oxide removal) creates a three-dimensional stepped structure that concentrates the electrical field in specific regions, thereby improving reading current and reducing stress time through enhanced field localization rather than uniform field distribution.
2Power
If conventional OTP memory device architecture is used, then fabrication cost is low, but reading current is weak
Solution Approach 1:
The patent selectively removes gate oxide only at corner regions to create second steps, while maintaining the first steps from STI removal across the substrate. This localized modification concentrates electrical field enhancement where most needed for reading operations, improving reading current without requiring comprehensive structural changes that would significantly increase fabrication cost.
Solution Approach 2:
The patent removes gate oxide partially (only at corners) rather than completely across the entire substrate. This partial action is sufficient to create the necessary electrical field concentration for improved reading current, while avoiding the excessive fabrication complexity and cost that would result from more extensive gate oxide removal or additional structural modifications.
3Duration of action of moving object
If conventional OTP memory device architecture is used, then device structure is simple, but stress time is long
Solution Approach 1:
The patent creates local step profiles by selectively removing STI and gate oxide at corner regions, concentrating electrical field enhancement where it most effectively reduces stress time. This localized approach achieves performance improvement without requiring complex structural modifications across the entire device, maintaining relative simplicity while reducing stress time.
Solution Approach 2:
The patent performs STI removal and gate oxide removal in advance during the fabrication process to pre-establish the stepped profiles before device operation. This preliminary action creates the electrical field concentration structure beforehand, enabling reduced stress time during actual device use without adding complexity to the operational device structure.
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of first providing a substrate comprising an one time programmable (OTP) device region, forming a shallow trench isolation (STI) in the substrate, removing part of the STI to form a first step on a corner of the substrate, forming a first gate oxide layer on the substrate, removing the first gate oxide layer to form a second step on the corner of the substrate, forming a second gate oxide layer on the substrate, and then forming a first gate structure on the substrate and the STI.