OTP Memory Cell Structure for Stable Anti-Fuse State Reading

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Solution Overview

Problem

Existing one-time-programmable (OTP) memory elements in integrated circuits face challenges in efficiently determining the programmed state due to variations in read voltage thresholds, leading to inaccuracies in data retention and retrieval.

Innovation Solution

The implementation of a novel OTP memory cell structure with a programmable anti-fuse device that includes a substrate, source and drain regions, and a gate oxide, where programming is achieved by breaking down the gate oxide to minimize resistance, and data is read based on current path presence or absence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a programming electric field is applied across the dielectric material layer to break it down and decrease resistance, then the anti-fuse bit is programmed, but variations in read voltage thresholds occur leading to inaccuracies in data retention and retrieval

Engineering Contradiction:
Improvedata retention reliabilityVSAvoidread voltage threshold precision
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

A reference cell with identical structure to the anti-fuse bit but without the programming electric field is introduced as an intermediary element. This reference cell provides a stable reference point for voltage comparison during read operations, eliminating the measurement precision issues caused by variations in read voltage thresholds. The reference cell allows accurate determination of the anti-fuse bit's programmed state through voltage differential measurement.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the gate oxide is broken down to minimize resistance for programming, then data can be read through current path detection, but the structure becomes more complex requiring additional reference cells

Engineering Contradiction:
Improvedata reading simplicityVSAvoidmemory cell structure complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The memory device is segmented into multiple identical anti-fuse bit cells and reference cells arranged in parallel. Each anti-fuse bit cell operates independently with its own programming and reading mechanism, while the reference cells provide distributed reference points. This segmentation allows the complex reference cell structure to be replicated and distributed, making the overall system more manageable and scalable despite the increased individual cell complexity.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Ensures reliable data retention and accurate data reading by distinguishing between programmed and un-programmed states through distinct current paths, enhancing the reliability and efficiency of OTP memory operations.

Implementation Method 1

a programming electric field is applied across the dielectric material layer to sustainably alter (e.g., break down) the dielectric material, thus decreasing the resistance of the dielectric material layer

Methodology Applied
Scientific EffectDielectric breakdown: Avalanche Breakdown

Implementation Method 2

a read voltage is applied across the dielectric material layer and a resultant current is read

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS12563721B2Memory device and method for forming the same
Publication Date: 2026.02.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12563721B2 patent drawing
  • US12563721B2 patent drawing
  • US12563721B2 patent drawing

AI summary

An OTP memory device includes a substrate, a first transistor, a second transistor, a first word line, second word line, and a bit line. The first transistor includes a first gate structure, and first and second source/drain regions on opposite sides of the first gate structure. The second transistor is operable in an inversion mode, and the second transistor includes a second gate structure having more work function metal layers than the first gate structure of the first transistor, and second and third source/drain regions on opposite sides of the second gate structure. The first word line is over and electrically connected to the first gate structure of the first transistor. The second word line is over and electrically connected to the second gate structure of the second transistor. The bit line is over and electrically connected to the first source/drain region of the first transistor.