OTP Memory Cell Verification and Redundancy Management
Solution Overview
Problem
One-time programmable (OTP) memory cells, particularly antifuse elements, require excessive voltages and currents for reliable programming, leading to high failure rates in end applications, which can result in field returns due to potential damage from high programming voltages and currents.
Innovation Solution
A memory device with a memory array comprising OTP cells and a memory controller that uses a pair of OTP cells to represent four states by storing data and supplementary data, with redundant cells reserved for failed cells, allowing for verification and replacement of failed cells to reduce failure rates through a programming and reading method that records states in supplementary cells and uses redundant cells for data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If antifuse elements are used for OTP memory cells, then reliable programming can be achieved, but excessive voltages and currents are required which may damage the surroundings
Solution Approach 1:
The patent performs preliminary verification of each OTP cell's programming status immediately after programming using a verification circuit. This preliminary action identifies failed cells before they can cause damage in end applications, allowing for early compensation using redundant cells.
Solution Approach 2:
The patent introduces supplementary cells as intermediary elements that store verification results. These supplementary cells act as a mediator between the data cells and redundant cells, enabling the system to track and compensate for failed cells without directly exposing end applications to the high voltage and current damage risks.
2Adaptability or versatility
If a portion of the array is reserved for programming by end users, then flexibility is provided, but the high failure rate due to excessive programming voltages and currents may cause field return
Solution Approach 1:
The system performs preliminary verification and compensation before end applications are deployed. By identifying and compensating for failed cells in advance using redundant cells, the system ensures high reliability for user-programmed portions while maintaining programming flexibility.
Solution Approach 2:
The patent applies different functions to different parts of the memory array: data cells for storage, supplementary cells for verification recording, and redundant cells for compensation. This local differentiation allows the user-programmable portion to maintain flexibility while the verification and compensation mechanisms ensure reliability.
3Reliability
If redundant cells are reserved for each set of data cells, then failure compensation is enabled, but storage space is consumed
Solution Approach 1:
Instead of reserving redundant cells for every single data cell, the patent reserves one redundant cell for each set of data cells (e.g., one redundant cell per 64 data cells). This partial redundancy approach provides sufficient failure compensation capability while minimizing storage space consumption.
Solution Approach 2:
The patent merges multiple data cells into sets, with one supplementary cell recording the verification status of each set, and one redundant cell compensating for failures in each set. This merging strategy reduces the overall number of redundant cells needed compared to individual cell redundancy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the failure rate of OTP memory devices by verifying and compensating for failed cells during programming and reading, ensuring data integrity with minimal impact on read latency and optimizing storage space by dynamically adjusting the number of reserved redundant cells based on failure rates.
Implementation Method 1
The OTP memory cells are typically implemented by antifuse, which relies on breakdown of metal-insulator-metal or diode structures to create two resistance states.
Data Source
AI summary
A memory device and methods for programming and reading a memory device are provided. The memory device includes a memory array and a memory controller. The memory array includes a plurality of one-time programmable (OTP) cells, in which the OTP cells comprises a plurality of data cells for storing data, a plurality of supplementary cells in parallel to the data cells, and one or more redundant cells for each of a plurality of sets of the data cells. The memory controller is configured to program the data cells. The memory controller verifies and records a state of each data cell in a set of the data cells in the corresponding supplementary cell after the programming, and stores the data to be programmed to the data cell using the one or more redundant cells reserved for the set of the data cells when the data cell is verified as failed.