OTP Memory Error Detection with Incremental Programming Check Bits

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Solution Overview

Problem

Existing OTP memories lack effective error detection mechanisms for incrementally programmed data, as Error Correction Codes (ECC) are not applicable, and redundant bits provide insufficient robustness for single-bit errors.

Innovation Solution

Implement programming check bits (PCBs) that can be incrementally generated and updated as data is programmed over time, combined with redundant bits to detect errors and differentiate between reliability issues and security attacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ECC check bits are stored with each data word in OTP memory, then error detection capability is improved, but the system cannot support incremental programming of data words

Engineering Contradiction:
Improveerror detection capabilityVSAvoidincremental programming capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The data word is segmented into multiple individual bits that can be programmed independently at different times. Each bit has its own programming check bit, allowing incremental programming while maintaining error detection capability for each individually programmed bit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Programming check bits (PCBs) are introduced as intermediary elements between the data bits and the error detection mechanism. These PCBs are generated and stored incrementally alongside the data bits, enabling error detection without requiring complete data word programming at once.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If redundant bits are used for error detection in OTP memory, then implementation simplicity is improved, but error detection robustness deteriorates compared to ECC

Engineering Contradiction:
Improveimplementation simplicityVSAvoiderror detection robustness
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The system changes the parameters of error detection by using programming check bits with specific logical combinations (XOR operations) of multiple data bits. This transforms the simple redundant bit approach into a more robust system that can detect multiple bit errors while maintaining incremental programming capability.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If all data bits and ECC check bits are programmed at once into OTP memory, then error detection robustness is improved, but incremental programming capability is lost

Engineering Contradiction:
Improveerror detection robustnessVSAvoidprogramming time flexibility
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Programming check bits are generated and stored preliminarily alongside data bits as they are individually programmed. This preliminary action enables error detection capability to be established incrementally, allowing data to be programmed over time rather than requiring complete programming at once.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12400731B2One-time-programmable (OTP) memory with error detection
Publication Date: 2025.08.26 NXP USA INC
  • US12400731B2 patent drawing
  • US12400731B2 patent drawing

AI summary

A controller for a one-time-programmable (OTP) memory is configured to, in response to a write request to program a single bit of an OTP value to the OTP memory, program a bit of the OTP value in the OTP memory, generate a set of PCBs corresponding to the OTP value, and program the PCBs into the OTP memory. Each PCB of the set of PCBs is generated as a logic function of a different subset of bits of the OTP value. The logic function only results in each PCB being programmed or remaining programmed in the OTP memory but not cleared. The OTP controller may be configured to, in response to the write request, program both the bit of the OTP value and a redundant bit, in which the set of PCBs includes a first PCB based on the bit and a second PCB based on the redundant bit.