OTP Memory ECC Gating for Redundancy Repair Address Integrity

Solution Overview

Problem

Existing semiconductor memory devices face reduced yield rates due to data errors caused by defective one-time programmable memories used for storing address information of defective memory cells, despite the implementation of Error Checking and Correcting (ECC) functions.

Innovation Solution

Incorporating a control unit that sets an ECC stop flag to prevent error detection and correction when inconsistent replacement address information and check information are present, ensuring accurate error detection and correction only when necessary, thereby improving yield rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error detection and correction is performed on all replacement address information, then data errors can be corrected, but unexpected errors are detected when inconsistent information is present, reducing yield rate

Engineering Contradiction:

Improvedata error correction capabilityVSAvoidyield rate

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The control unit performs preliminary verification to determine whether check information corresponding to the replacement address information is stored in the check memory before activating the error detection and correction unit. This preliminary action prevents unnecessary error detection and correction operations, avoiding false error detections that would reduce yield rate while maintaining data error correction capability when actually needed.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If ECC function is implemented in one-time programmable memory, then data errors in defective memory cells can be corrected, but the complexity of the memory system increases

Engineering Contradiction:

Improvedata error correctionVSAvoidmemory system complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The control unit performs preliminary verification to determine whether check information corresponding to the replacement address information is stored in the check memory before activating the error detection and correction unit. This preliminary action prevents unnecessary error detection and correction operations, avoiding false error detections that would reduce yield rate while maintaining data error correction capability when actually needed.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12547495B2Semiconductor memory device and controlling method thereof

Publication Date: 2026.02.10 WINBOND ELECTRONICS CORP

AI summary

A semiconductor memory device includes a memory unit and an error detection and correction unit. The memory unit is an OTP memory including a data memory and a check memory. The data memory is written with replacement address information detected during a redundancy repair operation and corresponding to a defective memory cell of a memory cell array. The check memory is written with check information detected during the redundancy repair operation and corresponding to the replacement address information. The error detection and correction unit performs error detection and correction on the replacement address information based on the check information. The data memory includes a unit accommodating the replacement address information. When other replacement address information and any of the replacement address information and the check information corresponding to the replacement address information are in the unit, the error detection and correction unit will not perform error detection and correction.