OTP Memory Cell Leakage Reduction via Segmented Regions
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Solution Overview
Problem
One-time programmable (OTP) memory devices face challenges with in-chip variation of electric characteristics and deterioration in program properties due to gate leakage current, which affects their performance and reliability.
Innovation Solution
The OTP memory device design includes a semiconductor substrate with write and read regions, junction patterns, and insulating dielectric patterns, where the write region has the same conductivity type as the junction patterns, and the read region has a different conductivity type, with the insulating dielectric patterns having a higher dielectric constant than silicon oxide, and gate spacers with decreasing width from the substrate, reducing gate leakage current and enhancing programming characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional OTP memory cell structure is used, then device complexity is reduced, but gate leakage current increases causing program property deterioration
Solution Approach 1:
The memory cell is divided into distinct write and read regions with separate junction patterns. The write region has first and second junction patterns with specific conductivity types, while the read region has different conductivity type junction patterns. This segmentation allows independent optimization of write and read operations, reducing gate leakage during programming while maintaining read functionality.
Solution Approach 2:
Different regions of the memory cell are assigned different conductivity types to optimize local performance. The write region uses junction patterns with conductivity types that minimize gate leakage during programming, while the read region uses different conductivity types optimized for read operations. This local quality differentiation resolves the contradiction between reducing gate leakage and maintaining program properties.
2Manufacturing precision
If write and read regions have the same conductivity type, then manufacturing is simplified, but in-chip variation of electric characteristics increases
Solution Approach 1:
The patent implements different conductivity types in write and read regions to reduce in-chip variation. The write region junction patterns have first and second conductivity types, while the read region junction patterns have different conductivity types. This local differentiation compensates for manufacturing variations by optimizing each region's electrical characteristics independently, achieving better overall uniformity despite increased structural complexity.
3Reliability
If gate insulating layer uses standard dielectric materials, then ease of manufacture is improved, but gate leakage current increases
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate insulating layer by selecting materials with higher dielectric constants than conventional silicon oxide. This parameter change reduces gate leakage current while maintaining manufacturability through standard semiconductor fabrication processes. The higher dielectric constant allows for thinner effective oxide equivalents, reducing tunneling current while keeping physical thickness compatible with existing manufacturing capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces gate leakage current and minimizes program property deterioration, resulting in improved in-chip variation and reliability of OTP memory devices.
Implementation Method 1
insulating dielectric patterns interposed between the write gate and the semiconductor substrate and between the read gate and the semiconductor substrate
Data Source
AI summary
A memory device including one-time programmable memory cells has a semiconductor substrate with a write region and a read region, a write gate provided on the write region, a read gate provided on the read region, first and second junction patterns provided at both sides of the read gate, and insulating dielectric patterns interposed between the write and read gates and the semiconductor substrate. The read region may have a different conductivity type from the first and second junction patterns, and the write region may have the same conductivity type as the first and second junction patterns.