OTP Memory Redundancy Scheme for In-System Repair
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Solution Overview
Problem
Conventional memory repair methods, such as using laser fuses or programmable resistive devices, are inefficient and costly due to large cell sizes, high voltages, and inability to scale with advancing CMOS technologies, making it difficult to perform in-system repairs and configurations.
Innovation Solution
Implementing a system with One-Time Programmable (OTP) memory cells that can store defective addresses and enable/disable bits within the memory chip, allowing for in-system repair and configuration using standard CMOS processes and low voltage supplies, enabling selection between normal and redundant memory cells based on programmed addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If laser fuses are used to store defective addresses, then memory repair capability is achieved, but cell size becomes large and cannot scale with shrinking MOS devices
Solution Approach 1:
The patent replaces the mechanical/optical laser fuse system with an electrical field-effect transistor (FET)-based OTP cell. Instead of using laser beams to melt polysilicon fuses, the invention uses electrical fields to control transistor conduction states, enabling programming through voltage application rather than optical energy. This substitution dramatically reduces cell size to match modern CMOS scaling while maintaining repair functionality.
Solution Approach 2:
The invention changes the programming mechanism from optical (laser) to electrical (voltage-controlled). By using voltage parameters to control FET conduction states (on/off) rather than optical energy to melt material, the cell dimensions can scale with standard CMOS processes. The electrical parameter approach enables integration with shrinking transistor dimensions without requiring large optical access areas.
2Reliability
If conventional OTP elements are used, then defective addresses can be stored, but high voltage supplies are required increasing system complexity
Solution Approach 1:
The patent changes the voltage parameter requirements by using standard CMOS-compatible voltage levels (e.g., 1.8V, 3.3V) instead of high voltages. The FET-based OTP cell uses gate voltage control to switch between conduction states, eliminating the need for external high-voltage generators, charge pumps, or specialized power supply circuits that conventional OTP elements require.
Solution Approach 2:
The FET-based OTP cell can be integrated into standard CMOS memory circuits without requiring separate high-voltage supply infrastructure. The same voltage rails used for normal memory operation can be used for OTP programming, making the system universally compatible with standard CMOS processes and eliminating additional complexity in power delivery networks.
3Reliability
If in-system repair is enabled, then memory chip reliability is improved, but additional circuitry and programming mechanisms are required
Solution Approach 1:
The patent merges the OTP programming circuitry with the existing memory write circuits. The same bitlines, wordlines, and sense amplifiers used for normal memory writes are also used for OTP programming. This consolidation eliminates the need for separate programming infrastructure, reducing device complexity while enabling in-system repair functionality.
Solution Approach 2:
The memory system performs its own repair operations using its existing resources. The OTP cells are programmed through the memory's own write interfaces without requiring external programming equipment or additional dedicated programming circuits. The system uses itself to configure and repair defective addresses, minimizing external dependencies and additional circuitry.
Data Source
AI summary
A novel redundancy scheme to repair no more than one defect per I/O in a One-Time-Programmable (OTP) memory is disclosed. An OTP memory has a plurality of OTP cells in a plurality of I/Os and at least one auxiliary OTP cell associated with each I/O. At least one volatile cell in each I/O corresponds to the auxiliary OTP cells. At least one Boolean gate to invert the data into and/or out of the main OTP memory in each I/O independently based on the data in the volatile cells. The data in each I/O of the OTP memory can be inverted if no more than one defect per I/O is found. Furthermore, the inversion scheme can be achieved by reading the auxiliary OTP cells and storing into the volatile cells by automatically generating at least one read cycle upon initialization.